实验九 硬件乐曲自动演奏电路设计.doc

验十 硬件乐曲自动演奏电路设计1、 实验目的：学习利用数控分频器设计硬件电子琴实验。2、 实验仪器：PC机，操作系统为Windows2000/xp, Quartus II 5.1 设计平台，GW48系列SOPE/EDA实验开发系统。3、 实验原理：本设计乐曲选取梁祝中化蝶部分，其简谱如图1所示。图1 梁祝中化蝶部分简谱组成乐曲的每个音符的发音频率值及其持续的时间是乐曲能连续演奏所需的2个基本要素，首先让我们来了解音符与频率的关系。乐曲的12平均率规定：每2个八度音(如简谱中的中音1与高音1)之间的频率相差1倍。在2个八度音之间，又可分为12个半音，每2个半音的频率比为。另外，音符A(简谱中的低音6)的频率为440Hz，音符B到C之间、E到F之间为半音，其余为全音。由此可以计算出简谱中从低音1至高音1之间每个音符的频率，如表1所示。表1 简谱中音符与频率的关系4、 主系统由4个模块组成；例1-1是顶层设计文件，其内部有三个功能模块（如图2所示）：Tone.VHD(例1-2)和Speaker.VHD（例1-3）及Notetabs.VHD（例1-4）.模块TONE是音阶发生器，当4位发声控制输入INDEX中某一位为高电平时，则对应某一音阶的数值将从端口TONE输出，作为获得该音阶的分频预置值；同时由CODE输出对应该音阶简谱的显示数码，如5，并由HIGH输出指示音阶高8度显示。由例6-28可见，其语句结构只是类似与真值表的纯组合电路描述，其中的音阶分频预置值，如Tone Indx, Tone=Tone2,CODE=CODE1,HIGH=HIGH1);u2 : Speaker PORT MAP (clk=CLK12MHZ,Tone1=Tone2, SpkS=SPKOUT );u3 : Notetabs PORT MAP(clk=CLK8HZ,Index0=Indx);END;【例10-2】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Tone IS PORT ( Index : IN INTEGER RANGE 0 TO 15; CODE : OUT INTEGER RANGE 0 TO 15; HIGH : OUT STD_LOGIC; Tone : OUT INTEGER RANGE 0 TO 16#7FF# );END;ARCHITECTURE one OF Tone ISBEGIN Search : PROCESS(Index) BEGIN CASE Index IS - 译码电路，查表方式，控制音调的预置数 WHEN 0=Tone = 2047; CODE = 0; HIGH Tone = 773; CODE = 1; HIGH Tone = 912; CODE = 2; HIGH Tone = 1036; CODE = 3; HIGH Tone = 1197; CODE = 5; HIGH Tone = 1290; CODE = 6; HIGH Tone = 1372; CODE = 7; HIGH Tone = 1410; CODE = 1; HIGH Tone = 1480; CODE = 2; HIGH Tone = 1542; CODE = 3; HIGH Tone = 1622; CODE = 5; HIGH Tone =1668; CODE = 6; HIGH Tone = 1728; CODE = 1; HIGH NULL; END CASE; END PROCESS;END;【例10-3】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Speaker IS PORT ( clk : IN STD_LOGIC; Tone1 : IN INTEGER RANGE 0 TO 16#7FF#; SpkS : OUT STD_LOGIC );END;ARCHITECTURE one OF Speaker IS SIGNAL PreCLK , FullSpkS : STD_LOGIC; BEGIN DivideCLK : PROCESS(clk) - 将CLK进 11分频，PreCLK为C L 11K 6分频 VARIABLE Count4 : INTEGER RANGE 0 TO 15; BEGIN PreCLK 11 THEN PreCLK = 1; Count4 := 0; ELSIF clkEVENT AND clk=1 THEN Count4 := Count4 + 1; END IF; END PROCESS; GenSpkS : PROCESS(PreCLK, Tone1) VARIABLE Count11 : INTEGER RANGE 0 TO 16#7FF#; BEGIN - 11位可预置计数器 IF PreCLKEVENT AND PreCLK = 1 THEN IF Count11=16#7FF# THEN Count11 := Tone1; FullSpkS = 1; ELSE Count11:=Count11 + 1; FullSpkS = 0; END IF; END IF; END PROCESS; DelaySpkS : PROCESS(FullSpkS) VARIABLE Count2 : STD_LOGIC; BEGIN IF FullSpkSEVENT AND FullSpkS = 1 THEN Count2 := NOT Count2; IF Count2 = 1 THEN SpkS = 1; ELSE SpkS = 0; END IF; END IF; END PROCESS;END;【例10-4】library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity Notetabs isPort ( clk: in std_logic; -系统时钟；键盘输入/自动演奏 index0 : out INTEGER RANGE 0 TO 15); -音符信号输出end NOTETABS;architecture Behavioral of Notetabs issignal count0:integer range 0 to 138;-changebeginmusic:process(clk) -此进程完成自动演奏部分曲的地址累加beginif clkevent and clk=1 thenif count0=138 then count0=0;else count0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0index0inde