晶片的来料检验

,PC issue inspection requisition,Box Label,Device typeLot noCustomer nameQuantity,Visual Sample,Packing conditionWafer QtyAny damage400x 100x,Dimension,ThicknessInk thickness,Complete InspectionReports,Incoming Wafer Inspection PQI004,Chipouts on edge of die shall not penetrate into any active circuit area. Note: Active circuit area is defined as from outside edge of the bond pads inward, except where there is an active line in the design located beyond the outside edge of the bond pads,Cracks,裂縫,碎片,邊緣,不可,穿透,線路,活性的,採納,報廢,Cracks shall not be longer than 1.0 mil inside active circuit area that points toward operating metal or functional circuit element.,裂縫,不可,超過限度,機能,線路,組成,Cracks that do not point toward operating metal or functional circuit elements shall not exceed 5.0 mils in length. (Silicon & GaAs Die),裂縫,指向,不,線路,活性的,不可,超過限度,Discoloration in glassivation outer layer is harmless and shall be acceptable, providing it is not obscuring any other damage.There shall be no corrosion in metallization, or any other layers.Metallization having any localized discoloration shall be closely examined and shall be rejected, unless it is demonstrated to be a harmless film, glassivation interface, or other non-obscuring effects.,Discoloration or Corrosion,變色,腐蝕狀態,玻璃鈍化,There shall be no Conductive (opaque) Foreign Material on the top of unglassivated die that is large enough to bridge two or more adjacent metallization areas, and that cannot be removed,Contamination or Foreign material,混淆,外來,料子,不透明,橋梁,Contamination or Foreign material,There shall be no conductive (opaque) Foreign Material under the top glassivation layer of the die that is large enough to bridge two or more adjacent metallization areas,There shall be no attached or embedded material in die that bridges two active circuit elements. GaAs: There shall be no attached or embedded material in die that reduces spacing of two active circuit elements by greater than 50 percent.Silicon: There shall be no attached or embedded material in die that does not provide a visible line of separation between two active circuit elements.,附加在.,深留,料子,There shall be no liquid drops, chemical stains, ink or photoresist on top of unglassivated areas that bridges two active circuit elements. (Liquid drops, chemical stains, ink or photoresist on top of glassivated portion of the die are acceptable).,液體,水滴,化學,污點,光致抗蝕劑,GaAs (requirement only)There shall be no cracking or chipping within active circuit area.There shall be no chipouts that extend beyond 50 percent of the substrate thickness or cracks in side walls greater than 5.0 mils.,Silicon: Shall have a visible line of separation between bond pads and/or operating metallization,Bridging and shorting,連結,短,路,墊,ACTIVE CIRCUIT All areas from outside edge of the bond pads inward, except where there is an active line in the design located beyond the outside edge of the bond pads.DIFFUSION - Electrical isolation of one or more active circuits.GLASSIVATION Top layer of transparent insulating material that covers active area except for bond pads.PASSIVATION LAYER - Insulating material on die prior to deposition of metal or between metal layers.Note: Some die by design may not have a glassivation layer.,Glassivation,There shall be no crazing or glassivation damage that prohibits visual inspection.There shall be no crazing or voids over a film resistor.There shall be no lifting or peeling more than 1.0 mil inside the active areas from the designed edge of the glassivation.,玻璃鈍化,There shall be no glassivation voids, cracks (not crazing) or scratches that exposes two or more adjacent active metallization paths.There shall be no unglassivated area greater than 5.0 mils.,There shall be no unglassivated area inside of active area which exposes bare semiconductor material.There shall not be glassivation over more than 25 percent of bond pad.,洞穴,裂縫,There shall be no diffusion fault that allows bridging between diffused areas.,放散,There shall be no breaks in diffusion (except isolation walls around unused areas or unused bonding pads).,There shall be no reduction of diffusion greater than 75 percent (50 percent for resistors) of original width. (except isolation walls around unused areas or unused bonding pads),There shall be no absence of glassivation over junction lines,Voids in the bonding pad shall not reduce metallization by more than 25 percent,Voids in the fillet area shall not reduce the metallization path width connecting the bond to the interconnecting metallization to less than 50 percent of the narrowest entering metallization stripe width.,洞穴,Scratches, probe marks, etc. in bond pads shall not remove more than 50 percent of the metal or expose underlying material,探討,印子,在下面的,Scratches in metal traces shall not result in any shorts.,There shall be no scratches in metal traces that result in a possible layer to layer short,Scratches or voids on metal traces shall not be greater than 50 percent of the trace width “W”.,Grounding areas may have small voids in the top metallization layer.Holes shall not penetrate sub-layers.Note: Adjusting of the microscope focus or dark vision will help in determining if sub-layers are penetrated.,There shall be no voids in any capacitors.,Active circuit metallization shall have no delam