数字电路英文版-第八单元ppt课件VIP

.,CHAPTER8FLIP-FLOPSANDRELATEDEDVICES,Astable(非稳态的)Hold-time(保持时间)Asynchronous(异步)Bistable(双稳态)Clear(清零)Dflip-flop(D触发器)Edge-triggeredflip-flop(边沿触发器)Feed-back(反馈)Hysteresis(迟滞)J-Kflip-flop(JK触发器)Latch(锁存器)Master-slaveflip-flop(主从触发器),Monostable(单稳态)One-shot(单稳)Preset(预置1)RESET(置0)SET(置1)Set-uptime(设置时间)S-Rflip-flop(RS触发器)Synchronous(同步)Timer(计时器)Toggle(触发,计数),KEYTERMS,AstableHavingnostablestate.Anastablemultivibratoroscillatesbetweentwoquasistablestates.AsynchronousHavingnofixedtimerelationship.BistableHavingtwostablestates.Flip-flopsandlatchesarebistablemultivibrators.,ClearAnasynchronousinputusedtoresetaflip-flop(maketheQoutput0).Dflip-flopAtypeofbistablemultivibratorinwhichtheoutputassumesthestateoftheDinputonthetriggeringedgeofaclockpulse.,Edge-triggeredflip-flopAtypeofflip-flopinwhichthedataareenteredandappearontheoutputonthesameclockedge.FeedbackTheoutputvoltageoraportionofitthatisconnectedbacktotheinputofacircuit.,HoldtimeThetimeintervalrequiredforthecontrollevelstoremainontheinputstoaflip-flopafterthetriggeringedgeoftheclockinordertoreliablyactivatethedevice.LatchAbistabledigitalcircuitusedforstoringabit.,HystersisAcharacteristicofathreshold-triggeredcircuit,suchastheSchmitttrigger,wherethedeviceturnsonandoffatdifferentinputlevels.J-Kflip-flopAtypeofflip-flopthatcanoperateintheSET,RESET,no-change,andtogglemodes.,Master-slaveflip-flopAtypeofflip-flopinwhichtheinputdataareenteredintothedeviceontheleadingedgesofclockpulsesandapperattheoutputontrailingedges.Master-slaveflip-flopshave,forthemostpart,beenreplacedbyedge-triggeredtypes.,MonostableHavingonlyonestablestate.Amonostablemultivibrator,commonlycalledaone-shot,producesasinglepulseinresponsetoatriggeringinput.One-shotAmonostablemultivibrator.PresetAnasynchronousinputusedtosetaflip-flop(maketheQoutput1).,RESETThestateofaflip-floporlatchwhentheoutputis0;theactionofproducingaRESETstate.SETThestateofaflip-floporlatchwhentheoutputis1;theactionofproducingaSETstate.,Set-uptimeThetimeintervalrequiredforthecontrollevelstobeontheinputstoadigitalcircuit,suchasaflip-flop,priortothetriggeringedgeofaclockpulse.S-Rflip-flopASET-RESETflip-flop.,SynchronousHavingafixedtimerelationship.ToggleTheactionofaflip-flopwhenitchangesstateoneachclockpulse.,.,8.1LATCHES,Thelatchisatypeoftemporarystoragedevicethathastwostablestates(bistable)andisnormallyplacedinacategoryseparatefromthatofflip-flop.,2.,Latchesarebasicallysimilartoflip-flopsbecausetheyarebistabledevicesthatcanresideineitheroftwostatesusingafeedbackarrangement,inwhichtheoutputsareconnectedbacktotheoppositeinputs.Themaindifferencebetweenlatchesandflip-flopisinthemethodusedforchangingtheirstate.,3.,.,TheS-R(SET-RESET)Latch,R,S,Q,Q,Active-HIGHinputS-Rlatch(NORS-RLatch),4.,.,Q,Q,S,R,5V,R,R,R,R,R,R,5.,.,S,R,Q,Q,(b)Active-LOWinputS-Rlatch(NANDS-RLatch),6.,.,S,R,Q,Q,WhenQisHIGH,QisLOW,andwhenQisLOW,QisHIGH.,7.,InputOutputs,SRQQComments,11NCNCNochange.latchremainsinpresentstate.,0110LatchSET.,1001LatchRESET.,0011Invalidcondition.,TABLE8-1Truthtableforanactive-LOWinputS-Rlatch.,8.,InputOutputs,SRQQComments,00NCNCNochange.latchremainsinpresentstate.,0101LatchRESET.,1010LatchSET.,1100Invalidcondition.,TABLE8-1Truthtableforanactive-HIGHinputS-Rlatch.,.,S,R,Q,Q,Active-HIGHinputS-Rlatch,S,R,Q,Q,(b)Active-LOWinputS-Rlatch,S,R,9.,.,EXAMPLE8-1,S,R,Q,10.,EXAMPLE8-1:RelatedProblemDeterminetheQoutputofanactive-HIGHinputS-Rlatchifthewaveformsinaboveareinvertedandappliedtotheinput.,S,R,Q,AlthoughSremainsLOWforonlyaveryshorttimebeforetheswitchbounce,thisissufficienttosetthelatch.,TheGatedS-RLatch,S,R,Q,Q,EN,S,R,EN,(a)Logicdiagram,(b)Logicsymbol,12.,ThelatchwillnotchangeuntilENisHIGH,butaslongasitremainsHIGH,theoutputiscontrolledbythestateoftheSandRinputs.,EXAMPLE8-2DeterminetheoutputwaveformiftheinputsshowninFig.8-9areappliedtoagatedS-RlatchthatisinitiallyRESET.,S,R,Q,EN,13.,Fig.8-9,(a),(b),EXAMPLE8-2:RelatedProblemDeterminetheQoutputofagatedS-RlatchiftheSandRinputsinFig.8-9(a)areinverted.,S,R,Q,EN,13.,Fig.8-9,(a),(b),TheGatedDLatch,D,Q,Q,EN,D,EN,(a)Logicdiagram,(b)Logicsymbol,14.,Q,Q,Qn+1=D,(S),(R),EXAMPLE8-3DeterminetheQoutputwaveformiftheinputsshowninFig.8-11(a)areappliedtoagatedDlatch,whichisinitiallyRESET.,D,Q,EN,15.,Fig.8-11,(a),EXAMPLE8-3RelatedProblemDeterminetheQoutputofthegatedDlatch,iftheDinputinFig.8-11(a)isreverted.,D,Q,EN,(a),InputOutputs,DENQQComments,0101RESET.,1110SET.,X0Q0Q0Nochange,Truthtable,16.,Qn+1=D,8.2EDGE-TRIGGEREDFLIP-FLOPS,Flip-flopsaresynchronousbistabledevices,alsoknownasbistablemultivibrators.Inthiscase,thetermsynchronousmeansthattheoutputchangesstateonlyataspecifiedpointonatriggeringinputcalledtheclock(CLK)whichisdesignatedasacontrolinputC;thatis,changesintheoutputoccurinsynchronizationwiththeclock.,17.,Edge-triggeredflip-flop:,S,R,Q,Q,C,D,Q,Q,C,J,K,Q,Q,C,S,R,Q,Q,C,D,Q,Q,C,J,K,Q,Q,C,Top:positiveedge-triggered;bottom:negativeedge-triggered.,18.,TheEdge-TriggeredS-RFlip-Flop:,S,R,Q,Q,C,InputsOutputs,00XQ0Q0Nochange,SRCLKQQComments,0101RESET,1010SET,11?Invalid,19.,Qn+1=S+RQn(SR=0condition),EXAMPLE8-4,S,R,Q,Q,C,1,2,3,4,5,6,S,R,Q,CLK,20.,EXAMPLE8-4DetermineQfortheSandRinputsinFig.8-16(a)iftheflip-flopisanegativeedge-triggereddevice.,1,2,3,4,5,6,S,R,Q,CLK,Pulse,transition,detector,Q,Q,S,R,CLK,0,1,HIGH(1),LOW(0),0,1,0,1,0,1,0,1,ThisgateisdisabledBecauseRisLOW.,Thisgateisenabled.,G4,G3,G2,G1,HIGH,Fig.8-18,21.,Pulse,transition,detector,Q,Q,S,R,CLK,0,1,HIGH(1),LOW(0),0,1,0,1,0,1,0,1,ThisgateisdisabledbecauseSisLOW.,Thisgateisenabled.,G4,G3,G2,G1,HIGH,Fig.8-19,22.,.,TheEdge-TriggeredDFlip-Flop:,S,Q,Q,C,D,CLK,InputsOutputs,110SET(1),DCLKQQComments,001RESET(0),23.,R,.,EXAMPLE8-5,D,Q,Q,C,1,2,3,4,Q,D,CLK,24.,1,2,3,4,Q,D,CLK,EXAMPLE8-5RelatedProblemDeterminetheQoutputfortheDflip-flopiftheDinputinFig.8-21(a)isreversed.,1,2,3,4,Q,D,CLK,EXAMPLE8-5RelatedProblemDeterminetheQoutputfortheDflip-flopiftheDinputinFig.8-21(a)isreversed.,TheEdge-TriggeredJ-KFlip-Flop:,J,K,Q,Q,C,InputsOutputs,00Q0Q0Nochange,JKCLKQQComments,0101RESET,1010SET,11Q0Q0Toggle,25.,Qn+1=JQn+KQn,InputsOutput,0000,JKQnQn+1,0011,0100,0110,1001,1011,1101,1110,Qn+1=JQn+KQn,1,J,KQn,00,01,11,10,0,1,0,1,2,3,4,5,6,7,1,1,1,1,0,J=XK=1,J=1K=X,J=XK=0,J=0K=X,InputsOutput,0000,SRQnQn+1,0011,0100,0110,1001,1011,110X,111X,S,RQn,00,01,11,10,0,1,0,1,2,3,4,5,6,7,1,1,0,S=0R=1,S=1R=0,S=XR=0,S=0R=X,1,1,X,X,Qn+1=S+RQn(SR=0condition),Pulse,transition,detector,Q,Q,J,K,Asimplifiedlogicdiagramforapositiveedge-triggeredJ-Kflip-flop.,G4,G3,G2,G1,CLK,26.,Pulse,transition,detector,Q,Q,J,K,TransitionsillustratingthetogglewhenJ=1andK=1.,G4,G3,G2,G1,CLK,1,2,3,HIGH,HIGH,1,2,3,1,2,3,1,2,3,27.,EXAMPLE8-6,1,2,3,4,5,CLK,J,K,Q,J,K,Q,Q,C,CLK,Toggle,No,change,Reset,Set,Set,28.,Fig.8-24,(a),EXAMPLE8-6RelatedProblemDeterminetheQoutputfortheJ-Kflip-flopiftheJ-KinputsinFig.8-24(a)arereversed.,1,2,3,4,5,CLK,J,K,Q,Fig.8-24,EXAMPLE8-6RelatedProblemDeterminetheQoutputfortheJ-Kflip-flopiftheJ-KinputsinFig.8-24(a)arereversed.,1,2,3,4,5,CLK,J,K,Q,Toggle,No,change,Reset,Set,Reset,AsynchronousPresetandClearInputs,J,K,Q,Q,C,PRE,CLR,LogicsymbolforaJ-Kflip-flopwithactive-LOWpresetandclearinputs.,29.,Pulse,transition,detector,PRE,CLR,Q,Q,J,K,CLK,LogicdiagramforabasicJ-Kflip-flopwithactive-LOWpresetandclear.,30.,.,J,K,Q,Q,C,PRE,CLR,EXAMPLE8-8:Forthepositiveedge-triggeredJ-Kflip-flop,determineQ.,HIGH,31.,2,1,3,4,5,6,7,8,9,CLR,PRE,Q,Preset,Toggle,Clear,32.,EXAMPLE8-8:RelatedProblemIfyouinterchangethePREandCLRwaveformsinFig.8-28(a),whattheQoutputlooklike.,2,1,3,4,5,6,7,8,9,CLR,PRE,Q,EXAMPLE8-8:RelatedProblemIfyouinterchangethePREandCLRwaveformsinFig.8-28(a),whattheQoutputlooklike.,2,1,3,4,5,6,7,8,9,CLR,PRE,Q,Preset,Toggle,Clear,83MASTER-SLAVEFLIP-FLOP,Anotherclassofflip-flopisthepulse-triggeredmaster-slave,whichhaslargelybeenreplacedbytheedge-triggereddevices.Althoughmaster-slaveflip-flopsareessentiallybecomingobsolete,youmayencounterthistypeofflip-flopinsomeexistingequipment.,33.,Dataareenteredintotheflip-flopattheleadingedgeoftheclockpulses,buttheoutputdoesnotreflecttheinputstateuntilthetrailingedge.Thepulse-triggeredmaster-slaveflip-flopdoesnotallowdatatochangewhiletheclockpulseisactive.,34.,ThePulse-TriggeredMaster-SlaveJ-Kflip-flop,G1,G2,S,R,Q,Q,G1,G2,S,R,Q,Q,C,J,K,CLK,Master,Slave,35.,.,InputsOutputs,00Q0Q0Nochange,JKCLKQQComments,0101RESET,1010SET,11Q0Q0Toggle,Truthtableforthemaster-slaverflip-flop,36.,J,K,Q,Q,C,J,K,Q,Q,C,(a)Active-HIGHclock:Dataareclockedinonpositive-goingedgeofclockpulseandtransferredtooutputonthefollowingnegative-goingedge.,(b)Active-LOWclock:Dataareclockedinonnegative-goingedgeofclockpulseandtransferredtooutputonthefollowingpositive-goingedge.,37.,.,EXAMPLE8-10:DeterminetheQoutputofthemaster-slaveJ-Kflip-flopfortheinputwaveformsshowninFig.,J,K,Q,Q,C,38.,.,5,6,7,8,9,2,1,3,4,K,J,Q,CLK,MaS,SlaS,MaNC,SlaNC,MaRE,SlaRE,MaNC,SlaNC,MaS,SlaS,MaRE,MaRE,SlaRE,SlaRE,MaS,MaS,SlaS,SlaS,SET,NC,NC,Toggle,Reset,39.,.,85FLIP-FLOPAPPLICATIONS,ApplicationExample,ParallelDataStorage:Acommonrequirementindigitalsystemsistostoreseveralbitsofdatafromparallellinessimultaneouslyinagroupofflip-flop.,40.,D,D,D,D,Q1,Q0,Q2,Q3,D0,D1,D2,D3,CLK,CLR,R,R,R,R,D0,D1,D3,D2,0,0,1,1,CLK,CLR,Q1,Q0,Q2,Q3,0,0,0,0,41.,0,0,1,1,CLR,Dstored,0,0,1,1,FrequencyDivision:Anotherapplicationofaflip-flopisdividingthefrequencyofaperiodicwaveform.,J,K,Q,C,HIGH,CLK,2,1,3,4,5,6,7,8,9,CLK,Q,42.,J,K,QA,C,HIGH,CLK,2,1,3,4,5,6,7,8,9,CLK,QA,J,K,QB,C,HIGH,QB,43.,J,K,QA,C,1,CLK,2,1,3,4,5,6,7,8,CLK,QA,J,K,QB,C,1,QB,Counting,1,1,0,1,1,0,1,0,0,1,0,0,0,0,1,1,0,3,2,0,1,1,2,3,Binarysequence,Binarysequence,EXAMPLE8-12:DeterminetheoutputwaveformsintherelationtotheclockforQA,QB,QCinthebelowcircuit.,J,K,QA,C,1,J,K,C,CLK,J,K,C,QB,QC,QA,QB,QC,44.,1,CLK,QA,QB,QC,1,1,1,1,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,45.,8.6ONE-SHOTS,Theone-shotisamonostablemultivibrator,adevicewithonlyonestablestate.Aone-shotisnormallyinitsstablestateandwillchangetoitsunstablestateonlywhentriggered.,46.,.,Onceitistriggered,theone-shotremainsinitsunstablestateforapredeterminedlengthoftimeandthenautomaticallyreturnstoitsstablestate.Thetimethatthedevicestaysinitsunstablestatedeterminesthepulsewidthofitsoutput.,47.,Trigger,t1,t1,t1,t1,t1,t2,t2,t2,t2,R,G1,G2,Q,+V,ApparentLOW,48.,Q,Q,Trigger,Q,Q,C,REXT,CEXT,Trigger,CX,RX/CX,+V,Basicone-shotlogicsymbols.CXandRXstandforexternalcomponents.,49.,NonretriggerableOne-Shots:Itwillnotrespondtoanyadditionaltriggerpulsesfromthetimeitistriggeredintoitsunstablestateuntilitreturnstoitsstablestate.,Trigger,Q,tw,(a),Trigger,Q,tw,Thesepulseareignoredbytheone-shot.,(b),50.,Theoutputpulsewidthissetbythevaluesoftheresistor(RINT=2k,andREXTisselected)andthecapacitoraccordingtothefollowingformula:,tw=0.7RCEXT,RiseitherRINTorREXT,51.,RetriggerableOne-Shots:Itcanbetriggeredbeforeittimesout.,Trigger,Q,tw,(a),Trigger,Q,tw,Retriggers,(b),52.,.,Ageneralformulaforcalculatingthevaluesofthesecomponentsforaspecifiedpulsewidth(tw)is,tw=0.32CEXT(1+0.7/R),53.,8.7THE555TIMER,The555timerisaversatileandwidelyuseddevicebecauseitcanbeconfiguredintwodifferentmodesaseitheramonostablemultivibrator(one-shot)orasanastablemultivibrator(oscillator).Anastablemultivibratorhasnostablestatesandthereforechangesbackandforth(oscillates)betweentwounstablestateswithoutanyexternaltriggering.,54.,+,_,+,_,R,S,Q,Q1,ComparatorA,ComparatorB,Threshold,Control,voltage,Trigger,Discharge,GND,Reset,Vcc,output,Discharge,transistor,R,R,R,(6),(8),(5),(2),(7),(1),(4),(3),55.,.,Monostable(One-Shot)Operation,tw=1.1R1C1,DISCH,RESET,THRESH,TRIG,OUT,CONT,GND,Vcc,Vcc,(8),(4),(7),(6),(2),(1),(5),(3),R1,C1,C2,56.,+,_,+,_,R,S,Q,Q1,A,B,Vcc,output,R,R,R,(6),(8),(5),(2),(7),(1),(4),(3),LOW,LOW,H-T,H,0V,LOW,(a)Priortotriggering,R1,ON,57.,+,_,+,_,R,S,Q,Q1,A,B,Vcc,R,R,R,(6),(8),(5),(2),(7),(1),(4),(3),LOW,0V,(b)Whentriggered,t0,t0,t0,t0,Vc1,0,R1,OFF,58.,Output,+,_,+,_,R,S,Q,Q1,A,B,R,R,R,(6),(5),(2),(7),(1),(4),LOW,0V,(c)Atendofcharginginterval,t0,t0,t1,t0,VCC,0,R1,ON,t1,t1,t1,HIGH,2,3,59.,.,AstableOperation,DISCH,RESET,THRESH,TRIG,OUT,CONT,GND,Vcc,Vcc,(8),(4),(7),(6),(2),(1),(5),(3),R1,C1,C2,60.,R2,+,_,+,_,R,S,Q,Q1,A,B,R,R,R,(6),(5),(2),(7),(1),(4),(3),0V,Operationofthe555timerintheastablemode,R1,ON,Charging,Discharging,R2,61.,2/3Vcc,1/3Vcc,(1),(1),.,Thefrequencyofoscillationisgivenbythefollowingformula.,f=,1.44,(R1+2R2)C1,(8-4),ThetimethattheoutputisHIGH(tH)ishowlongittakesC1tochargefrom1/3Vccto2/3Vcc.,tH=0.7(R1+R2)C1,(8-5),62.,.,ThetimethattheoutputisLOW(tL)ishowlongittakesC1todischargefrom1/3Vccto2/3Vcc.,tL=0.7R2C1,(8-6),T=tH+tL=0.7(R1+2R2)C1,Dutycycle=,tH,T,tH,tH,tL,+,63.,.,Dutycycle=100%,R1+R2,R1+2R2,64.,(8-7),Dutycycle=100%,R1,R1+R2,DISCH,RESET,THRESH,TRIG,OUT,CONT,GND,Vcc,Vcc,(8),(4),(7),(6),(2),(1),(5),(3),R1,C1,C2,D1,65.,(8-8),R2,+,_,+,_,R,S,Q,Q1,A,B,R,R,R,(6),(5),(2),(7),(1),(4),VI,Schmitt-TriggerFF,VCC,59.,6,8,4,7,2,3,5,555,(0),6,8,4,7,2,3,5,555,(0),R3,R2,R1,S,20k,5V,10uF,C2,C1,0.01uF,0.01uF,0.22uF,C3,2.4k,tw=10sf=1.2kHzFindR1,R2,6,8,4,7,2,3,5,555,(0),6,8,4,7,2,3,5,555,(0),R3,R2,R1,S,20k,5V,10uF,C2,C1,0.01uF,0.01uF,0.22uF,C3,2.4k,tw=10sf=1.2kHzFindR1,R2,OneShot:tw=1.1R1C1(83),Astablemultivibrator:f=1.44/(R2+2R3)C2(8-4),Chapter8:Flip-FlopandRelatedDevices,True/False,Allmultivibratorsrequirefeedback.Multivibratorsmustbeleveltriggered.Edge-triggeredflip-flopscanbeidentifiedbythetriangleontheclockinput.ADflip-flopisconstructedbyconnectinganinverterbetweentheSetandClockterminals.,5.TheJ-Kflip-flopeliminatestheinvalidstatebytogglingwhenbothinputsarehighandtheclocktransitions.6.PresetandClearinputsarenormallysynchronous.7.Whenusingmaster-slaveflip-flops,thedataisenteredintotheflip-flopontheleadingedgeoftheclock,buttheoutputdoesnotchangeuntilthetrailingedgeoftheclock.8.Pulse-triggeredflip-flopsareidentifiedbyabubbleontheQoutputterminal.,9.Aone-shotisaspecialtypeofmultivibratorwhichmustbetriggeredtoproduceeachoutputpulse.10.The555timercanbeusedineithertheastableormonostablemodes.MultipleChoice:11.Anactive-HIGHinputS-Rlatchhasa1ontheSinputanda0ontheRinput,whatstateisthelatchin?Q=1,Q=0b.Q=1,Q=1c.Q=0,Q=1d.Q=0,Q=0,12.WhatadvantagedoesaJ-Kflip-flophaveoveraR-Sflip-flop?Ithasfewergates.Ithasonlyoneoutput.Ithasnoinvalidstates.Itdoesnotrequireaclockinput.,13.WhatisonedisadvantageofaR-Sflip-flop?IthasnoEnableinput.Ithasaninvalidstates.IthasnoCLOCKinput.Ithasonlyasingleoutput.,14.HowistheinvalidstateproblemassociatedwiththeR-Sflip-flopovercome?TheRterminaliseliminated.TheRinputisfedthroughaninverter.Asingleinputterminalisused(D).Bothbandcarecorrect.,15.WhichofthefollowingiscorrectforagatedDlatch?Theoutputtogglesifoneoftheinputsisheldhigh.QoutputfollowstheinputDwhentheENABLEishigh.Onlyoneoftheinputscanbehighatatime.Theoutputcomplementfollowstheinputwhenenabled.,16.Whichsymbolisusedtoidentifyedge-triggeredflip-flops?AbubbleontheClockinput.Aninverted“L“ontheoutput.TheletterEontheEnableinput.AtriangleontheClockinput.,17.Edge-triggeredflip-flopsmusthaveveryfastresponsetimes.atleasttwoinputstohandlerisingandfallingedges.apulsetransitiondetector.active-lowinputsandcomplementedoutputs.,18.Whichofthefollowingdescribestheoperationofapositiveedge-triggeredDflip-flop?Ifbothinputsarehigh,theoutputwilltoggle.Theoutputwillfollowtheinputontheleadingedgeoftheclock.Whenbothinputsarelow,aninvalidstatewillexist.Theinputistoggledintotheflip-flopontheleadingedgeoftheclockandispassedtotheoutputonthetrail