FPGA片上资源-FDR FDRE FDRS FDRSE 说明.docx

FPGA片上资源-FDR/FDRE/FDRS/FDRSE 2010-11-23 17:47FDR : D Flip-Flop with Synchronous Reset/itp/xilinx5/data/docs/lib/lib0170_154.htmlSpartan-II,Spartan-IIESpartan-3Virtex,Virtex-EVirtex-II,Virtex-II Pro,Virtex-II Pro XXC9500/XV/XLCoolRunnerXPLA3CoolRunner-IIPrimitivePrimitivePrimitivePrimitiveMacroMacroFDR is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low during the Low-to-High clock transition.The flip-flop is asynchronously cleared, output Low, when power is applied.MacroFDR is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low during the Low-to-High clock transition.The flip-flop is asynchronously cleared, output Low, when power is applied.VHDL Inference Codearchitecture Behavioral of fdr isbeginprocess (C) beginif (C event and C = 1) thenif (R = 1) thenQ = 0;elseQ = D;end if;end if;end process;end Behavioral;Verilog Inference Codealways (posedge C) begin if (R) Q = 0; else Q = D;endFDRE : D Flip-Flop with Clock Enable and Synchronous Reset /itp/xilinx5/data/docs/lib/lib0172_156.htmlFDRE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low and CE is High during the Low-to-High clock transition.The flip-flop is asynchronously cleared, output Low, when power is applied.VHDL Inference Codearchitecture Behavioral of fdre isbeginprocess (C) beginif (C event and C = 1) thenif (R = 1) thenQ = 0;elsif (CE = 1) thenQ = D;end if;end if;end process;end Behavioral;Verilog Inference Codealways (posedge C) begin if (R) Q = 0; else if (CE) Q = D;endFDRS : D Flip-Flop with Synchronous Reset and Set/itp/xilinx5/data/docs/lib/lib0174_158.htmlFDRS is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-High clock (C) transition. (Reset has precedence over Set.) When S is High and R is Low, the flip-flop is set, output High, during the Low-to-High clock transition. When R and S are Low, data on the (D) input is loaded into the flip-flop during the Low-to-High clock transition.The flip-flop is asynchronously cleared, output Low, when power is applied.VHDL Inference Codearchitecture Behavioral of fdrs isbeginprocess (C) beginif (C event and C = 1) thenif (R = 1) then Q = 0;elsif (S = 1) thenQ = 1;elseQ = D;end if;end if;end process;end Behavioral;Verilog Inference Codealways (posedge C) begin if (R) Q = 0; else if (S) Q = 1; else Q = D;endFDRSE : D Flip-Flop with Synchronous Reset and Set and Clock Enable/itp/xilinx5/data/docs/lib/lib0176_160.htmlFDRSE is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). The reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-High clock transition. (Reset has precedence over Set.) When the set (S) input is High and R is Low, the flip-flop is set, output High, during the Low-to-High clock (C) transition. Data on the D input is loaded into the flip-flop when R and S are Low and CE is High during the Low-to-High clock transition.The flip-flop is asynchronously cleared, output Low, when power is applied.VHDL Inference Codearchitecture Behavioral of fdrse isbeginprocess (C) beginif (C event and C = 1) t