5.-Cortex-M3指令集

CortexM3Thumb-2指令集,李宁武汉理工大学,Agenda,IntroductionGeneralPointsonSyntaxDataprocessingInstructionsBranchandControlFlowInstructionsMemoryAccessInstructionsExceptionGeneratingInstructionsAccessingSpecialRegistersCoprocessorInstructionsMemoryBarriersandSynchronizationFurtherInformation,ARMinstructionsetevolution,KeyTechnologyAdditionsbyArchitectureGeneration,TheThumb-2instructionset,Variable-lengthinstructionsARMinstructionsareafixedlengthof32bitsThumbinstructionsareafixedlengthof16bitsThumb-2instructionscanbeeither16-bitor32-bitCodesizebenefitsThumb-2givesapproximately26%improvementincodedensityoverARMPerformancebenefitsThumb-2givesapproximately25%improvementinperformanceoverThumbTheCortex-M3implementsONLYtheThumb-2instructionset,Syntax,IntheCortex-M3instructionset,thereareoftenseveralpossiblewaysofencodingagivenoperationSyntaxspecifiessemanticsWherethereismorethanonepossibleinstructionforgivensemanticsAssemblyrulesAlwayspicksmallestinstructionExceptforexternalbrancheswhichchooselargestCanuse.N/.Wtoforce16or32bitinstruction(e.g.foralignment)DisassemblyrulesOne-to-onemappingisdefinedtoensurecorrectre-assembly.W/.NsuffixusedforcaseswhenabitpatternwhichdoesntfollowtheaboverulesisdisassembledBinaryoperatorsalwaysdisassembleto3-operandformsExceptforsomecasesof2-operandThumbADDAvoiduseofr13,r14,r15usesp,lr,pcinstead,Registerusage,Ingeneral,allregistersaregeneral-purpose,exceptforthefollowing.r13isusedastheStackPointeranditsusagereflectsthisSPmanipulationrestrictedtoMovementbetweenspandanothergeneral-purposeregisterUsingADDorSUBtoadjustitbyamultipleof4e.g.ADDsp,sp,#N;Nmustbemultipleof4e.g.SUBSP,SP,Rm,LSL#shift;shift=0-3AsfirstoperandinADD,SUB,CMP,CMNIngeneral,SPcannotbeloadedfrommemoryWherethisispermitted,thisisnotedinthispresentationSPwillbeautomaticallyrestrictedtoword-alignedvaluesHardwarewillignorewritestobits0and1PCisgenerallynotpermittedasanoperand,exceptas:BaseregisterinLDRBaseregisterinTBB/TBHDestinationforLDR,orinthelistforPOP/LDM,Exampleassemblersourcefile,AREAARMEX,CODE,READONLYENTRYTHUMBmainMOVr0,#10MOVr1,#3ADDr2,r0,r1;thisisacommentstopBstopdataDCD0 x11,0 x22,0 x33END,Arithmeticinstructions,ThefollowingarithmeticinstructionareavailableADDADCSUBSBCRSBANDBICEORORRORNGeneralsyntaxADDSRd,Rn,op2op2canbeAnimmediateconstantADDr0,r1,#0 x21AnotherregisterwithanoptionalshiftADDr0,r1,r2,LSL#3TheSsuffixcontrolswhethertheinstructionupdatestheconditioncodeflagsbasedontheresultInsomeinstructionsitisoptional,inotherseithercompulsoryornotallowedatall,Constants,AnimmediateconstantcantakeseveralformsAnyconstantproducedby8bitsshiftedleftbyupto32bitsThisallowsany8consecutivebitstobesettoanyvalueReplicatedhalfwordofform0 x00XY00XYReplicatedhalfwordofform0 xXY00XY00Replicatedbyteconstantofform0 xXYXYXYXYAttemptstouseconstantswhicharenotofthisformwillgenerateanassemblyerrorTherearespecialformsofADDandSUBwhichallowlargerconstantsADDWRd,Rm,#imm12;adds12-bitconstantSUBWRd,Rm,#imm12;subtracts12-bitconstant,Availableshiftoperations,Destination,CF,0,Destination,CF,LSL:LogicalShiftLeft,ASR:ArithmeticShiftRight,Multiplicationbyapowerof2,Divisionbyapowerof2,preservingthesignbit,Destination,CF,.0,Destination,CF,LSR:LogicalShiftRight,ROR:RotateRight,Divisionbyapowerof2,BitrotatewithwraparoundfromLSBtoMSB,Destination,RRX:RotateRightExtended,SinglebitrotatewithwraparoundfromCFtoMSB,CF,Datamovement,ThereareanumberofinstructionsformovingbetweenoneregisterandanotherorsettingaregistertoaconstantMOVSRd,#imm;Rd=#immMOVSRd,Rm,shift;Rd=RmwithoptionalshiftMVNhasidenticalsyntaxtoabovebutmoveslogical1scomplementSpecialformscanuselargerconstantsMOVWRd,#imm16;setlower16bitsofregisterand;clearupperhalfwordMOVTRd,#imm16;settop16bitsofregister,Usefulpseudoinstructions,TheassemblerprovidessomeusefulpseudoinstructionsforloadingvaluesintoregistersLoadingacompile-timeconstantintoaregisterLDRRn,=AssemblerwilluseoptimalinstructionsequencetogenerateconstantintospecifiedregisterLoadinganaddressintoaregisterADRRn,AssemblerwillusePC-relativeADDorSUBtogeneratetheaddressofthelabelintothespecifiedregisterADRLisavailableforreferencesoutsidethecurrentsectionThesearetherecommendedmechanismsforgeneratingconstantsintoregisters,TestandCompareinstructions,TheseinstructionsalwayschangetheconditioncodeflagsCMPRn,#imm;compareRnwithconstantCMPRn,Rm,shift;comparewithregisterCMNhassamesyntaxbutcompareswith2scomplementofoperandTEQperformsa“logicalEOR”betweenitsoperandsUsedfortestingforequalitywithoutchangingVflag(asCMPdoes)TSTperformsa“logicalAND”betweenitsoperandsUsedfortestingwhetheroneormorebitsinasubsetissetAlsofortestingwhetherasinglebitissetorclear,Shift/rotateinstructions,TheshiftandrotatefeaturesarealsoavailableviaseparateinstructionsTheseinstructionscanrotateorshifteitherbyaconstantdistanceorbyavariabledistancecontrolledbyanotherregisterTheshift/rotatedistanceistakenfromtheleastsignificantbyteofRmLSRSRd,Rn,#3;Rd=Rn3LSRSRd,Rn,Rm;Rd=RnRmLSL,ASRandRORarealsoavailableTheseinstructionscanoptionallychangetheconditioncodeflags,BitManipulationInstructions,0,31,0,0,0,0,0,0,0,0,1,0,1,0,1,1,0,0,0,0,0,1,1,1,0,1,0,0,0,31,0,0,0,0,0,0,0,0,1,0,1,0,1,1,0,0,0,1,1,0,1,0,0,0,0,0,1,0,1,0,1,1,BFIBitFieldInsert,UBFXUnsignedBitFieldExtract,BFCBitFieldClear,0,RBITReverseBitOrder,Fordetailsofsyntax,seethedocumentation,1,CountLeadingZeros,CLZRd,RmReturnsnumberofbinaryzerobitsbeforethefirstbinaryonebitinaregistervalueSourceregisterisscannedfrommostsignificantbittoleastsignificantbitExecutesin1-cycleResultis32ifnobitsset,zeroifbit31issetUsedinsoftwaredivideandfloatingpointroutinesLeftshiftofRmbyRdwillnormalizeRmSignednormalizerequires1extracycle,0000001011101101.0,R0=,CLZR1,R0,0 x6,R1=,1011101101000000.0,Rm=,MOVR0,R0,LSLR1,EORR1,R0,R0,LSL#1CLZR1,R1MOVR0,R0,LSLR1,Thereare2classesofmultiply-producing32-bitand64-bitresultsMULr0,r1,r2;r0=r1*r2MLAr0,r1,r2,r3;r0=r3+(r1*r2)MLSr0,r1,r2,r3;r0=r3-(r1*r2)64-bitmultiplyinstructionsofferbothsignedandunsignedversionsFortheseinstructionthereare2destinationregistersU|SMULLr4,r5,r2,r3;r5:r4=r2*r3U|SMLALr4,r5,r2,r3;r5:r4=(r2*r3)+r5:r4TherearesignedandunsignedintegerdivisioninstructionsSDIVRd,Rn,RmUDIVRd,Rn,Rm,MultiplyandDivide,Saturatinginstructions,AlthoughCortex-M3doesnotsupportsaturatedarithmetic,theseinstructionsareusefulfordetectingoverflowofsub-wordquantitiesSSATRd,#bit,Rn,shift;saturateRnat#bitTheoptionalshiftcanbeanydistancebutisrestrictedtoLSLorASRUSATdoesthesamewithunsignedvalues0 x00004E74Saturatedtobit16isunchangedbecauseitislessthan216-1Saturatedtobit8,theresultis0 xFFsinceitisgreaterthan28-1,Unchanged,Saturated,Qflagset,Byteordering,ThefollowinginstructionsareusefulwheninterfacingwithadevicewhoseendiannessdiffersfromthatofthecoreREVRd,Rm;reversebyteorderREV16Rd,Rm;reversesbyteorderinhalfwords;separately(2301inaboveexample)REVSHRd,Rm;reversesbyteorderinlowerhalfword;andsignextends(SS01inaboveexample),ByteandHalfwordextraction,SXTBRd,Rm,rotExtracts8-bitvalueandsignextendsto32bitsOptionalRORallowsanybytetobeextracted,SXTHextractsahalfwordandsignextendsUnsignedformsdonotsignextendUXTB,UXTHGeneralOnlyROR#8,#16or#24arepermitted,Quiz,Whatdothefollowinginstructionsdo?ADDSr0,r1,#5BICr0,r0,#0 xFF00Writeinstructionstocarryoutthefollowingoperations:r0=r0+0 x456r1=r24Arethefollowingconstantsvalidwithdataprocessinginstructions?5.0 x1FF7.0 x84006.0 x120012008.0 xFFFFFFFF,Simplebranchinstructions,BranchescanbePC-relativeorabsolutePC-relativebranchinstructionshavethefollowingformatsBlabelBranchrangeis16MBifunconditional,1MBifconditional,AlsohaveabsolutebranchtoaddressinregisterBXRn;unconditionalonly,Conditioncodes,ThepossibleconditioncodesarelistedbelowNoteAListhedefaultanddoesnotneedtobespecified,Subroutines,ImplementingaconventionalsubroutinecallrequirestwostepsStorethereturnaddressBranchtotheaddressoftherequiredsubroutineThesestepsarecarriedoutinoneinstruction,BLThereturnaddressisstoredinthelinkregister(lr/r14)Branchrangeis16MBReturningisperformedusingBXtobranchbacktotheaddressstoredinlr,CanalsobranchtoaddressinregisterBLXRn;unconditionalonly,Branchtables,TBBr0,r1,offset1,offset2,offset3,offset4,offsetn,+,pc,destination,Theseinstructionscanbeusedtoimplementsimplebranchtables,pccanbeusedasthebaseregister,allowingthetabletobeplacedinlineMaximumbranchrangeis+514bytesfromcurrentinstructionTBHindexesanarrayofhalfwordoffsetsinthesameway,offsetbyr1,x2,CompareandBranch,ComparewithzerofollowedbyabranchisacommonsequenceTraditionally,thisinvolvestwoseparateinstructionsCBZreplacesthesewithoneinstruction,Maximumbranchrangeis+130bytesBranchisforwardsonlyCBNZbranchesontheNEconditionbutisotherwisethesame,If.ThenConditionalBlocks,TheIf.Theninstructioncanbeusedtogenerateblocksofuptofourinstructionsdependentonasinglevalueoftheconditioncodeflags,;if(r0=0);r0=*r1+2;else;r0=*r2+4;ifCMPr0,#0ITTEEEQ;thenLDREQr0,r1ADDEQr0,#2;elseLDRNEr0,r2ADDNEr0,#4,Withintheblock,itisgoodpracticetousetheexplicitconditioncodesoneachinstructionTheITinstructionitselfdoesnotchangetheconditioncodesUnlessspecified,instructionswithintheblockdonotchangethecodeseitherIngeneral,youshouldnotbranchintooroutofanITblockAbranchmaybewrittenasthefinalinstructionSVCmaybeusedanywhereITblockscannotbenested,Quiz,WhatisthedifferencebetweenBandBL?WheredoesBLstorethereturnaddress?Whatistheusualreturninstructionfromasubroutine?Whichhasalongerbranchrange,conditionalorunconditional?WhatisthesizeofeachtableentryinaTBBinstruction?Whichinstructioncanbeusedtoreplaceacompareandaconditionalbranch?HowmanyinstructionscanbemadeconditionalusingIT?,Singleregisterdatatransfer,LDRSTRWordLDRBSTRBByteLDRHSTRHHalfwordLDRSBSignedbyteloadLDRSHSignedhalfwordloadMemorysystemmustsupportallaccesssizesSyntax:LDRRd,STRRd,Notethatmemoryaccessinstructionsdonotupdatetheconditioncodeflags,Addressaccessed,TheaddressaccessedbyLDR/STRisspecifiedbyabaseregisterplusanoffsetTheoffsetcanbeAn8-bitimmediatevaluewhichmaybeaddedorsubtractedLDRr0,r1,#8LDRr0,r1,#-12A12-bitoffset(whichmayonlybeadded)Anotherregister,whichmaybeoptionallyshifted0-3placesleftandaddedLDRr0,r1,r2LDRr0,r1,r2,LSL#2Choiceofpre-indexedorpost-indexedaddressing,0 x5,0 x5,0 x200,r1,BaseRegister,0 x200,0 x5,r0,SourceRegisterforSTR,12,Offset,0 x20c,0 x200,r1,OriginalBaseRegister,0 x200,0 x5,r0,SourceRegisterforSTR,12,Offset,0 x20c,0 x20C,r1,UpdatedBaseRegister,Auto-updateform:STRr0,r1,#12!,PreorPostindexedaddressing?,Pre-indexed:STRr0,r1,#12,Post-indexed:STRr0,r1,#12,Only8-bitconstantoffsetscanbeusedwithpost-indexedaddressing,Load/StoreDouble,LDRDandSTRDtransfertworegistersatatimeMoreefficientthattwoseparateLDR/STRinstructionsFewinstructionfetchesMaymakeuseofsequentialbustransactionsLDRDRd1,Rd2,Rn,#offset!Positiveornegative8-bitoffsetismultipliedby4beforeuseWritebackispossiblebutRncannotbeoneofthedestinationregistersDestinationregistersmustbedifferentLDRDRd1,Rd2,Rn,#offsetPositiveornegative8-bitoffsetismultipliedby4beforeuseAllregistersmustbedifferentSTRDSameaddressingmodesSourceregisterscanbethesameWritebackispossiblebutRnmustnotbeeitherofthesourceregisters,TheLoadandStoreMultipleinstructions(LDM/STM)allowbetween2and16registerstobetransferredtoorfrommemoryOrderofregisterstransferscannotbespecifiedMusthaveatleast2registersinthelistLowestregisternumberisalwaystransferredto/fromlowestmemorylocationaccessedLDMIAr10,r0,r1,r4BaseregisterspecifieswherememoryaccessshouldoccurTheseinstructionsareveryefficientforMovingblocksofdataLDM/STMcanbeinterruptedWillbecontinuedonreturnifpossible,elserestarted,Blockdatatransfers,r10,IncreasingAddress,LDM/STMoperation,Syntax:Rb!,2addressingmodes:LDMIA/STMIA-incrementafterLDMDB/STMDB-decrementbefore,IA,r1,IncreasingAddress,r4,r0,r10,DB,LDMxxr10,r0,r1,r4STMxxr10,r0,r1,r4,BaseRegister(Rb),TheSTM/LDMinstructionscanbeusedforefficientblockcopyingofmemoryForexample;r8pointstostartofsourcedata;r9pointstoendofsourcedata;r10pointstostartofdestinationdataloopLDMIAr8!,r0-r7;load32bytesSTMIAr10!,r0-r7;andstorethemCMPr8,r9;checkfortheendBLTloop;andloopInthisexample8wordsarecopiedperloop,Memoryblockcopying,Stackinstructions,Forstackoperations,therearededicatedPUSHandPOPinstructionsTheseimplementaFullDescendingstackusingr13asthestackpointerTheyareactuallysynonymsforLDMIAandSTMDBPUSHreglistPushesalistofregistersontothestackPOPreglistPopsalistofregistersoffthestackNotethatPUSH/POPwithonlyoneregisterinthelistareencodedusingLDR/STRratherthanLDM/STMe.g.PUSHr0willuseSTRr0,sp,#-4!Inthissituation,LDR/STRarequickerthanLDM/STM,Thestackinoperation,100,FF,1234,A0BE,8034,OperationofaFullDescendingstackTheinstructionsshownarecommonatentryandexitofCprocedures,PUSHr4-r7,lr,Exclusiveloadandstore,Instructionswhichtagamemoryaccessas“exclusive”LDREXRd,Rn,#offsetOperation:Rd=*RnSTREXRd,Rm,Rn,#offsetOperation:*Rn=Rm;Rd=0ifmemoryupdated,else1CLREX;clearsanyrecordofexclusiveaccessforthisprocessorCanbeusedtoimplementOSsemaphoresRequiresmemorysystemsupportonmulti-processorsystemsMOVr1,#0 xFF;loadlocktakenvaluetry_for_lockLDREXr0,LockAddr;loadlockvalueCMPr0,#0;islockfree?STREXEQr0,r1,LockAddr;yes,sotrytoclaimCMPEQr0,#0;succeeded?BNEtry_for_lock;no,sotryagainDMB;yes-nowhavelock,somakesureeveryone;elseknowsaboutitbeforecontinuing,Memoryaccesssizeandalignment,TheARMmemorysystemistreatedasalineararrayofbyteswhichcanbeaccessedaswordsAccesses,ingeneral,mustbealignedonanappropriateboundaryAllalignasexpectedexceptthatdoublewordaccessesrequireonlywordalignmentUnalignedaccessescanresultinavarietyofhardwarebehaviorTheunalignedbitsoftheaddresscanbemaskedandtheaccesstreatedasalignedTheunalignedaccesscanbesupportedinhardwareAppliesonlytowordandhalfwordLDRandSTRandtoTBHAllothertypesofmemoryaccessalwaysgenerateanalignmentfaultGenerateanalignmentfault,Quiz,WhichARMload/storeinstructionsallowyoutoexpresstheaddressasaconstant?WhataretheadvantagesofLDM/STMoverLDR/STR?Whichregisterisusedasthestackpointer?Whichinstructionswouldyouusetoimplementasemaphore?Whichaccesssizesmustthememorysystemsupport?,Exceptiongeneratinginstructions,SVC(formerlySWI)CausesaSystemCallexceptionHandledbythesystemviatheexceptionvectortableUsedtogetaccesstoprivilegedoperationsBKPTCausesentrytodebugstateFaultsifdebugisdisabled(withHardFault)UsedforsemihostingAlwaysunconditional,eveninsideanITblock,Readingspecialregisters,TheMRSinstructionreadsspecialregistersintoageneral-purposeregisterMRSRd,stack_pointerReadsMSPorPSPMRSRd,status_regReadsIPSR,EPSR,APSR,IEPSR,IPSR,EAPSR,PSRMRSRd,mask_regReadsPRIMASK,BASEPRI,BASEPRI_MAX,FAULTMASKMRSRd,control_regReadsCONTROLGeneralUsermodecannotreadanystackpointerorIPSRzeroswillbereturnedAllEPSRbitsreadaszeroduringnormalexecutionbutcanbereadwheninhaltingdebugmode,Writingspecialregisters,TheMSRinstructioncopiesageneral-purposeregistertoaspecialregisterMSRstatus_reg,RnWritesIPSR,EPSR,APSR,IEPSR,IAPSR,EAPSRorPSRMSRstack_pointer,RnWritesMSPorPSPMSRmask_reg,RnWritesPRIMASK,BASEPRI,BASEPRI_MAXorFAULTMASKMSRcontrol_reg,RnWritesCONTROLGeneralUsermodeisonlyallowedtowriteFPSR,anythingelsewillbeignoredIPSRandEPSRarenotwriteableBASEPRI_MASKoptionupdatestheBASEPRImaskregisteronlywhenthenewvalueincreasestheprioritylevel,Someshortcuts,TheCPSinstructionprovidessomeshorthandforcommonoperationsCPSIEiEquivalenttosettingPRIMASKto0CPSIDiEquivalenttosettingPRIMASKto1CPSIEfEquivalenttosettingFAULTMASKto0CPSIDfEquivalenttosettingFAULTMASKto1,Coprocessorinstructions,TheinstructionsetcontainsspaceforoperationsinvolvingexternalcoprocessorsMRC,MCR,MCRR,MRRCTransferregistersbetweencoreandcoprocessorCDPInstructscoprocessortocarryoutadataprocessingoperationLDC,STCAllowscoprocessordirectload/storeaccesstomemoryFaultsIfthespecifiedcoprocessorisnotpresent,thecorewillgenerateanNOCPUsageFaultAnunrecognisedcoprocessorinstructionwillcauseanUNDEFINSTRUsageFaultForthesyntaxofthese,consultthedocumentation,Memorybarriers,DMBEnsureallmemoryaccessesduetopreviousinstructionswillcompletebeforeanyaccessesduetosubsequentinstructionsNotethatthisensuresorderingofaccesse