VHDL流水线加法器可编程实验报告

.可编程实验报告实验报告要求：1、任务的简单描述2、画出电路图3、写出源代码4、仿真结果5、分析和讨论1、3-8译码器源代码：LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_signed.all;ENTITY dc38 ISPORT(sel:instd_logic_vector(2 downto 0);y:outstd_logic_vector(7 downto 0);END dc38;ARCHITECTURE behavior OF dc38 ISBEGINy=11111110 WHEN sel = 000 else11111101 WHEN sel = 001 else11111011 WHEN sel = 010 else11110111 WHEN sel = 011 else11101111 WHEN sel = 100 else11011111 WHEN sel = 101 else10111111 WHEN sel = 110 else01111111 WHEN sel = 111 elseZZZZZZZZ;END behavior;仿真结果：一位全加器 A B CI S CO 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1四级流水加法器一位全加器 第 一 级 锁 存 器 第 三 级 锁 存 器 一位全加器第 二 级 锁 存 器一位全加器 第 四 级 锁 存 器一位全加器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity adder isport(clk,rst : in std_logic;a,b : in std_logic_vector(3 downto 0);sum : out std_logic_vector(3 downto 0);c : out std_logic);end entity adder;architecture depict of adder issignal reg1: std_logic_vector(7 downto 0);signal reg2: std_logic_vector(6 downto 0);signal reg3: std_logic_vector(5 downto 0);beginbit0:process(clk,rst)beginif(rst=1) thenreg1=00000000;elsif(rising_edge(clk) thenreg1(0)= a(0) xor b(0); reg1(1)= a(0) and b(0);reg1(2)= a(1); reg1(3)= b(1);reg1(4)= a(2);reg1(5)= b(2);reg1(6)= a(3);reg1(7)= b(3);end if;end process bit0;bit1:process(clk,rst)beginif(rst=1) thenreg2=0000000;elsif(rising_edge(clk) thenreg2(0)= reg1(0);reg2(1)= reg1(1) xor reg1(2) xor reg1(3);reg2(2)= (reg1(1) and reg1(2)or(reg1(1)and reg1(3)or(reg1(2)and reg1(3);reg2(6 downto 3)=reg1(7 downto 4);end if; end process bit1;bit2:process(clk,rst)beginif(rst=1) thenreg3=000000;elsif(rising_edge(clk) thenreg3(1 downto 0)=reg2(1 downto 0);reg3(2)=reg2(2)xor reg2(3)xor reg2(4);reg3(3)=(reg2(2)and reg2(3)or(reg2(2)and reg2(4)or(reg2(3)and reg2(4);reg3(5 downto 4)=reg2( 6 downto 5);end if;end process bit2;bit3:process(clk,rst)beginif(rst=1) thensum=0000;c=0;elsif(rising_edge(clk) thensum(2 downto 0)=reg3(2 downto 0);sum(3)=reg3(3)xor reg3(4)xor reg3(5);c=(reg3(3)and reg3(4)or(reg3(3)and reg3(5)or(reg3(4)and reg3(5);end if;end process bit3;end depict;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity noadd isport(clk,rst : in std_logic;a,b : in std_logic_vector(3 downto 0);sum : out std_logic_vector(3 downto 0);c : out std_logic);end entity noadd;architecture depict of noadd issignal reg : std_logic_vector(4 downto 0);signal rega: std_logic_vector(4 downto 0);signal regb: std_logic_vector(4 downto 0);beginprocess(clk) beginif(rising_edge(clk)thenrega=0& a;regb=0& b; end if;end process;process(clk)beginif(rst=1)thenreg=00000;elsif(rising_edge(clk)thenreg=rega+regb;end if;end process;sum=reg(3 downto 0);c=reg(4);end depict;4位十进制数计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity dec_disp is port(clk_cnt : in std_logic;sel1 : out std_logic_vector(3 downto 0);sel2 : out std_logic_vector(3 downto 0);sel3 : out std_logic_vector(3 downto 0);sel4 : out std_logic_vector(3 downto 0);end dec_disp;architecture behav of dec_disp issignal data1 : std_logic_vector(3 downto 0);signal data2 : std_logic_vector(3 downto 0);signal data3 : std_logic_vector(3 downto 0);signal data4 : std_logic_vector(3 downto 0);begin count:process(clk_cnt) begin if(rising_edge(clk_cnt)then if(data1=1001)then data1=0000; else if(data2=1001)then data2=0000; data1=data1+1; else if(data3=1001)then data3=0000; data2=data2+1; else if(data4=1001)then data4=0000; data3=data3+1; else data4=data4+1; end if; end if; end if; end if;end if;end process count;sel1=data1;sel2=data2;sel3=data3;sel4=data4;end behav;正弦波发生器 .sin.mif文件depth=256;width=8;address_radix=dec;data_radix=dec;contentbegin 0: 131; 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