电子科技大学《数字逻辑设计及应用》lec17-cha

1,DigitalLogicDesignandApplicatonLecture#17,LatchesandFlip-Flops,UESTC,Spring2013,2,再谈串行输入加法器的实现,CLK,电平有效还是边沿有效？,串行输入、串行输出注意：时钟同步,IterativeVs.Sequential,3,IterativeVersusSequentialCircuits,C0,C4,X0Y0,X1Y1,X2Y2,X3Y3,S0,S1,S2,S3,4,7.2LatchesandFlip-Flops,Latcheschangeitsoutputsatanytime(enableinputisasserted).Flip-Flopschangeitsoutputsonlywhentheclockchanges,Positive-EdgeRising-Edge,Negative-dgeFalling-Edge,Leveltriggered,Edge-triggered,ET,5,7.2.5Edge-TriggeredDFlip-Flops,WhenCLK=0,WhenCLK=1,QmfollowsD;Qisunchanging.,Qmisunchanging,Q=QmuntilthenextrisingCLKedge,1.Master/Slave,Positive-edge-triggered,QchangesonlywhenCLKrisesfrom0to1,6,TimingDiagramformaster-slaveDF/F,Q=D(),7,8,DLatch,DFlip-Flopedge-triggered,whenCLKisasserted,对信号扰动不敏感,受信号扰动影响,9,Dflip-floptimingparameters,Propagationdelay(fromCLK),Setuptime(DbeforeCLK）Holdtime(DafterCLK),D,CLK,Q,在时钟上升边沿附近有一个时间窗口，在此窗口时间内，数据输入D不能改变，否则电路进入亚稳态。,从输入信号D到来时刻至信号D达到稳定所持续的时间。,从输入信号D达到稳定至信号D被锁存器接受所持续的时间。,10,2.Negative-Edge-TriggedDFlip-Flop,3.DFlip-Flopwithpresetandclear,同步(synchronous)是指与时钟同步，即时钟触发条件满足时检测清零(置位)信号是否有效，有效则在下一个时间周期的触发条件下，执行清零(置位)；异步(asynchronous)是清零(置位)信号有效时，无视触发脉冲，立即清零(置位)。,11,12,3.DFlip-Flopwithpresetandclear,asynchronousinputsbehaviorlikethesetandresetinputsonS-Rlatch.,1,0,0,1,1,1,1,1,0,1,1,13,TimingDiagramforDflip-flopwithpresetandclear,3.DFlip-Flopwithpresetandclear,synchronousinputs:PR(preset)andCLR(cleardependontheCLK,14,Reset,CLK,?,R有效，Q=0R无效，Q=Din,15,4.CommercialTTLDFlip-Flops(74LS74),P535Figure7-20,PR_L,CLR_L,CLK,D,Q,QN,维持阻塞结构,Smallerandfaster,16,5.CMOSedge-triggeredDcircuit,Usestransmissiongatesinfeedbackloops,Q,D,CLK,D,CLK,Twofeedbackloops(masterandslavelatches),17,7.2.6DFlip-FlopwithEnable,IfENisasserted,theexternalDinputisselected;ifENisnegated,thecurrentoutputisused.,18,7.2.7ScanFlip-Flop,TE=0,DisselectedTE=1,TIisselected,19,TO,TI,CLK,TE,WhenTEisnegated,Q=D,20,7.2.8Master/SlaveS-RFlip-Flop,21,Master/SlaveS-RFlip-FlopTimingDiagram,暂时忽略延迟时间等动态特性,C,unpredictable,unpredictable,22,C,Edge-Triggered?,unpredictable,TheS-Rflip-flopchangesitsoutputsonlyatthefallingedgeofC.,Butitisnottrulyedgetriggered.,Pulse-Triggeredflip-flops,23,7.2.8Master/SlaveS-RFlip-Flop,postponed-outputindicator,dynamicinputindicatoredgetriggered,24,7.2.9Master/SlaveJ-KFlip-Flop,消除主从S-R触发器存在的约束条件,利用反馈消除主从S-R触发器存在的约束条件,S=JQR=KQmeetSR=0,J-KFFCharacteristicEquation,Q*=JQ+(KQ)Q,(K+Q)Q,KQ,25,7.2.10Edge-TriggeredJ-KFlip-Flop,J-KFF:Q*=JQ+KQ,DFF:Q*=D,26,7.2.11TFlip-Flop,ATflip-flopchangesstateoneverytickoftheclock.,27,DesignaTFlip-Flop,UsingaDflip-flopDFF:Q*=DTFF:Q*=QD=Q,UsingaJ-Kflip-flopJK:Q*=JQ+KQT:Q*=QJ=K=1,28,TFlip-FlopwithEnable,T：Q*=ENQ+ENQ,JK：Q*=JQ+KQ,D：Q*=D,29,7.2.11TFlip-Flop,说明：传统中文教材中认为：T触发器的特征方程Q*=TQ+TQT=1时翻转；T=0时维持,30,关于电路结构和逻辑功能,同一功能的触发器可用不同电路结构实现主从结构的D触发器、维持阻塞结构的D触发器同类电路结构可做成不同功能的触发器维持阻塞结构的：D触发器、J-K触发器,31,SummariesofLatchandFlip-Flop,Latch:outputchangeswhenCLKisassertedFlip-Flop: