VHDL双语教学第2章.ppt

VHDL,Simulationuseieee.std_logic_1164.all;-entityXYZis-Canputanythingafterthe-port(A1,A2,A3:instd_logic;F:outstd_logic);endXYZ;-architectureXYZ_archofXYZisbeginF=(A1andA2)or(A2andA3)or(A1andA3);endXYZ_arch;,ABC,A1A2A3,F,A1A2A3,F,FileXYZ.VHD,VHDLinQuartus,Synthesisuseieee.std_logic_1164.all;-entityXYZisport(A,B,C:instd_logic;-CommentsF:outstd_logic);endXYZ;-architectureXYZ_archofXYZisbeginF=(AandB)or(BandC)or(CandA);endXYZ_arch;,XYZ.VHD(2)dataflow,libraryieee;useieee.std_logic_1164.all;-entityXYZisport(A,B,C:instd_logic;F:outstd_logic);endXYZ;-architectureXYZ_archofXYZisbeginF=1when(A=1)and(B=1)else1when(B=1)and(C=1)else1when(A=1)and(C=1)else0;endXYZ_arch;,XYZ.VHD(3)behavioral,libraryieee;useieee.std_logic_1164.all;-entityXYZisport(A,B,C:instd_logic;F:outstd_logic);endXYZ;-architectureXYZ_archofXYZisbeginprocess(A,B,C)beginif(A=1)and(B=1)thenF=1;elsif(B=1)and(C=1)thenF=1;elsif(A=1)and(C=1)thenF=1;elseF=0;endif;endprocess;endXYZ_arch;,XYZ.VHD(4)structural,libraryieee;useieee.std_logic_1164.all;libraryaltera;usealtera.maxplus2.ALL;-entityXYZisport(A,B,C:instd_logic;F:outstd_logic);endXYZ;-architectureXYZ_archofXYZissignalF1,F2,F3:std_logic;beginU1:and2portmap(A,C,F1);U2:and2portmap(A,B,F2);U3:and2portmap(B,C,F3);F=F1orF2orF3;endXYZ_arch;,XYZAllinOneBlockDiagram,XYZ(Entity),ABC,F,XYZ_arch1,XYZ_arch2,XYZ_arch3,XYZ_arch4(Architecture),XYZ.VHD(AllinOne),libraryieee;useieee.std_logic_1164.all;LIBRARYaltera;USEaltera.maxplus2.ALL;-*entityXYZisport(A,B,C:instd_logic;F:outstd_logic);endXYZ;-*architectureXYZ_arch1ofXYZisbeginF=(AandB)or(BandC)or(CandA);endXYZ_arch1;-,architectureXYZ_arch2ofXYZisbeginF=1when(A=1)and(B=1)else1when(B=1)and(C=1)else1when(A=1)and(C=1)else0;endXYZ_arch2;-architectureXYZ_arch3ofXYZisbeginprocess(A,B,C)beginif(A=1)and(B=1)thenF=1;elsif(B=1)and(C=1)thenF=1;elsif(A=1)and(C=1)thenF=1;elseF=0;endif;endprocess;endXYZ_arch3;-,architectureXYZ_arch4ofXYZissignalF1,F2,F3:std_logic;beginU1:and2portmap(A,C,F1);U2:and2portmap(A,B,F2);U3:and2portmap(B,C,F3);F=F1orF2orF3;endXYZ_arch4;-,XXYYZZ,XXYYZZ,XYZ,MY_PACKAGE.VHD,libraryieee;useieee.std_logic_1164.all;-packagemy_packageiscomponentXYZisport(A,B,C:instd_logic;F:outstd_logic);endcomponent;endmy_package;,XXYYZZ.VHD,libraryieee;useieee.std_logic_1164.all;librarywork;usework.my_package.all;-entityXXYYZZisport(A1,A2,B1,B2,C1,C2:instd_logic;F:outstd_logic);endXXYYZZ;-architectureXXY