计算机组成与结构

,计算机组成与结构,Lecture20层次结构的存储器Reading:7.1-7.3Homework:7.1-7.4,7.9,7.12,7.14,7.39,本课件内容源于美国Lafayette大学JohnNestor教授的课件,ECE313Fall2006,Lecture20-Memory,2/89,Roadmapfortheterm:majortopics,Overview/AbstractionsandTechnologyInstructionsetsLogic&arithmeticPerformanceProcessorImplementationSingle-cycleimplemenatationMulticycleimplementationPipelinedImplementationMemorysystems3Input/Output,ECE313Fall2006,Lecture20-Memory,3/89,Outline-MemorySystems,Overview3MotivationGeneralStructureandTerminology(术语)MemoryTechnologyStaticRAMDynamicRAMDisksCacheMemoryVirtualMemory,ECE313Fall2006,Lecture20-Memory,4/89,MemorySystems-theBigPicture,MemoryprovidesprocessorwithInstructionsDataProblem:memoryistooslowandtoosmall,ECE313Fall2006,Lecture20-Memory,5/89,MemoryHierarchy-theBigPicture,Problem:memoryistooslowandtoosmallSolution:memoryhierarchy（层次）-分层存储器,Fastest,Slowest,Smallest,Biggest,Highest,Lowest,ECE313Fall2006,Lecture20-Memory,6/89,WhyHierarchyWorks,Theprincipleoflocality（局部性原理）Programsaccessarelativelysmallportionoftheaddressspaceatanyinstantoftime.-在任一瞬间，程序只访问地址空间中的一小部分Temporallocality:recentlyaccesseddataislikelytobeusedagainSpatiallocality:datanearrecentlyaccesseddataislikelytobeusedsoonResult:theillusion(幻想)oflarge,fastmemory,ECE313Fall2006,Lecture20-Memory,7/89,MemoryHierarchy-Speedvs.Size,ECE313Fall2006,Lecture20-Memory,8/89,MemoryHierarchyTerminology术语,Processor,BlocksofData,数据复制每次只在两个相邻层次间进行,ECE313Fall2006,Lecture20-Memory,9/89,存储器层次结构的几个术语,Hit:处理器需要的数据出现在高层的某个块中(greenblock)HitRate:thefractionofmemoryaccessesthat“hit”HitTime:timetoaccesstheupperlevel(timetodeterminehit/miss+accesstime)Miss:datamustberetrievedfromblockinlowerlevel(orangeblock)缺失率MissRate=1-(HitRate)MissPenalty:Timetoreplaceblockinupperlevel+TimetodeliverdatatotheprocessorHitTimeMissRate,ECE313Fall2006,Lecture20-Memory,10/89,TypicalMemoryHierarchy-Details,Registers-Small,fasteston-chipstorageManagedbycompilerandrun-timesystemCache-Small,faston-chipstorageAssociativelookup-managedbyhardwareMemory-Slower,Largeroff-chipstorageLimitedsize16Gb-managedbyhardware,OSDisk-Slowest,Largestoff-chipstorageVirtualmemorysimulatealargememoryusingdisk,hardware,andoperatingsystemFilestorage-storedatafilesusingoperatingsystem,ECE313Fall2006,Lecture20-Memory,11/89,存储器系统影响计算机的许多方面,用于构造存储器系统的概念影响到计算机的许多方面，如：OS对存储器和I/O如何管理编译器如何生成代码应用程序如何使用计算机性能评估因而，设计人员花费了相当的精力开发复杂的机制以提高存储器系统的性能本章进行了大量抽象和简化,ECE313Fall2006,Lecture20-Memory,12/89,Outline-MemorySystems,OverviewMotivationGeneralStructureandTerminologyMemoryTechnology3StaticRAMDynamicRAMCacheMemoryVirtualMemory,ECE313Fall2006,Lecture20-Memory,13/89,MemoryTypes,StaticRAMStorageusinglatchcircuits(门锁电路）ValuessavedwhilepoweronDynamicRAMStorageusingcapacitors（电容）Valuesmustberefreshed,bit,bit,word/rowselect,1,0,0,1,word/rowselect,bit,C,ECE313Fall2006,Lecture20-Memory,14/89,Tradeoffs-Staticvs.DynamicRAM,StaticRAM(SRAM)-usedforL1,L2cacheFast-0.5-25nsaccesstime(lessforon-chip)Larger,MoreExpensiveHigherpowerconsumptionDynamicRAM(DRAM)-usedforPCmainmemorySlower-80-250nsaccesstime*Smaller,CheaperLowerpowerconsumption,ECE313Fall2006,Lecture20-Memory,15/89,DRAMOrganization,RowDecoder,ColumnSelector/Latch/IO,RowAddress,ColumnAddress,/RAS,/CAS,DATA,ECE313Fall2006,Lecture20-Memory,16/89,DRAMReadOperation,RowDecoder,ColumnSelector/Latch/IO,RowAddress,ColumnAddress,/RAS,/CAS,DATA,ECE313Fall2006,Lecture20-Memory,17/89,DRAMTrends（趋势）,RAMsize:4Xevery3yearsRAMspeed:2Xevery10years,DRAMYearSizeCycleTime198064Kb250ns1983256Kb220ns19861Mb190ns19894Mb165ns199216Mb145ns199564Mb120ns1997?128Mb?ns1999?256Mb?ns,1980-1995Sizechange:1000:1!,1980-1995Speedchange:2:1!,ECE313Fall2006,Lecture20-Memory,18/89,TheProcessor/MemorySpeedGap,DRAM9%/yr.(2X/10yrs),1,10,100,1000,1980,1981,1983,1984,1985,1986,1987,1988,1989,1990,1991,1992,1993,1994,1995,1996,1997,1998,1999,2000,DRAM,CPU,1982,Processor-MemoryPerformanceGap:(grows50%/year),Performance,Time,“MooresLaw”,ECE313Fall2006,Lecture20-Memory,19/89,定位导致速度差异的原因AddressingtheSpeedGap,LatencydependsonphysicallimitationsBandwidthcanbeincreasedusing:并行Parallelismtransfer(传输)morebits/wordBursttransfers-transfersuccessivewordsoneachcycle在每个周期中传输连续的机器字So.usebandwidthtosupportmemoryhierarchy(层次)!UsecachetosupportlocalityofreferenceDesignhierarchytotransferlargeblocksofmemory,ECE313Fall2006,Lecture20-Memory,20/89,CurrentDRAMParts,Synchronous同步的DRAM(SDRAM)-clockedtransferofburstsofdatastartingataspecificaddressDouble-DataRateSDRAM-transfertwobits/clockcycleQuad（方形）-DataRateSDRAM-transferfourbits/clockcycleRambusRDRAM-High-speedinterfaceforfasttransfersCurrentPCsusesomeformofSDRAM/RDRAMSDRAMw/PC100orPC133memorybusRDRAMw/PC800memorybus,ECE313Fall2006,Lecture20-Memory,21/89,MemoryConfigurationinCurrentPCs,Processor,SystemController,L1Cache,MainMemory(DRAM),L2/L3Cache(SRAM),(I/OBus),ECE313Fall2006,Lecture20-Memory,22/89,主存是以存储芯片为基本单位构成,用16K1位的存储芯片组成64K8位的存储器,32片,ECE313Fall2006,Lecture20-Memory,23/89,存储芯片的译码驱动方式-线选法,ECE313Fall2006,Lecture20-Memory,24/89,存储芯片的译码驱动方式-重合法,0,0,ECE313Fall2006,Lecture20-Memory,25/89,静态RAM(SRAM)基本电路,A触发器非端,A触发器原端,T1T4,ECE313Fall2006,Lecture20-Memory,26/89,静态RAM基本电路的读操作,ECE313Fall2006,Lecture20-Memory,27/89,静态RAM基本电路的写操作,ECE313Fall2006,Lecture20-Memory,28/89,静态RAM芯片举例-Intel2114,存储容量1K4位,这些存储元件应该如何排列？才能给出一个存储单元的地址而一次读出4位信息。1、立体；2、平面,ECE313Fall2006,Lecture20-Memory,29/89,Intel2114RAM矩阵(6464)读,ECE313Fall2006,Lecture20-Memory,30/89,Intel2114RAM矩阵(6464)读,ECE313Fall2006,Lecture20-Memory,31/89,Intel2114RAM矩阵(6464)读,ECE313Fall2006,Lecture20-Memory,32/89,Intel2114RAM矩阵(6464)读,ECE313Fall2006,Lecture20-Memory,33/89,Intel2114RAM矩阵(6464)读,ECE313Fall2006,Lecture20-Memory,34/89,Intel2114RAM矩阵(6464)读,ECE313Fall2006,Lecture20-Memory,35/89,Intel2114RAM矩阵(6464)读,ECE313Fall2006,Lecture20-Memory,36/89,Intel2114RAM矩阵(6464)读,ECE313Fall2006,Lecture20-Memory,37/89,Intel2114RAM矩阵(6464)读,ECE313Fall2006,Lecture20-Memory,38/89,Intel2114RAM矩阵(6464)写,ECE313Fall2006,Lecture20-Memory,39/89,Intel2114RAM矩阵(6464)写,ECE313Fall2006,Lecture20-Memory,40/89,Intel2114RAM矩阵(6464)写,ECE313Fall2006,Lecture20-Memory,41/89,Intel2114RAM矩阵(6464)写,ECE313Fall2006,Lecture20-Memory,42/89,Intel2114RAM矩阵(6464)写,ECE313Fall2006,Lecture20-Memory,43/89,Intel2114RAM矩阵(6464)写,ECE313Fall2006,Lecture20-Memory,44/89,Intel2114RAM矩阵(6464)写,ECE313Fall2006,Lecture20-Memory,45/89,Intel2114RAM矩阵(6464)写,ECE313Fall2006,Lecture20-Memory,46/89,Intel2114RAM矩阵(6464)写,ECE313Fall2006,Lecture20-Memory,47/89,动态RAM(DRAM)-基本单元电路,读出与原存信息相反,读出时数据线有电流为“1”,写入与输入信息相同,写入时CS充电为“1”放电为“0”,T,无电流,有电流,ECE313Fall2006,Lecture20-Memory,48/89,动态RAM芯片举例-三管动态RAM芯片(Intel1103)读,读写控制电路,ECE313Fall2006,Lecture20-Memory,49/89,三管动态RAM芯片(Intel1103)写,ECE313Fall2006,Lecture20-Memory,50/89,三管动态RAM芯片(Intel1103)写,ECE313Fall2006,Lecture20-Memory,51/89,三管动态RAM芯片(Intel1103)写,ECE313Fall2006,Lecture20-Memory,52/89,三管动态RAM芯片(Intel1103)写,ECE313Fall2006,Lecture20-Memory,53/89,三管动态RAM芯片(Intel1103)写,ECE313Fall2006,Lecture20-Memory,54/89,三管动态RAM芯片(Intel1103)写,ECE313Fall2006,Lecture20-Memory,55/89,三管动态RAM芯片(Intel1103)写,读写控制电路,ECE313Fall2006,Lecture20-Memory,56/89,三管动态RAM芯片(Intel1103)写,读写控制电路,ECE313Fall2006,Lecture20-Memory,57/89,三管动态RAM芯片(Intel1103)写,读写控制电路,ECE313Fall2006,Lecture20-Memory,58/89,存储器与CPU的连接-存储器容量的扩展,用2片1K4位存储芯片组成1K8位的存储器,ECE313Fall2006,Lecture20-Memory,59/89,(2)字扩展（增加存储字的数量）,用2片1K8位存储芯片组成2K8位的存储器,ECE313Fall2006,Lecture20-Memory,60/89,(3)字、位扩展,用8片1K4位存储芯片组成4K8位的存储器,ECE313Fall2006,Lecture20-Memory,61/89,存储器与CPU的连接的一般步骤,(1)地址线的连接：首选低位地址；,(2)数据线的连接：位数要相等；,(3)读/写线的连接：直接相连；,(4)片选线的连接：MREQ和空闲的高地址组合,(5)合理选用芯片：RAM/ROM分清,(6)其他时序、负载,Attention:地址线不可悬空，多余的地址线作为控制线，地址线的特定组合决定控制逻辑的设计,ECE313Fall2006,Lecture20-Memory,62/89,例题：,设CPU有16根地址线，8根数据线，用MREQ（低电平有效）作访存控制信号，用WR作读/写控制信号（高电平为读，低电平为写）。现有如下存储芯片：1Kx4位RAM；4Kx8RAM；8Kx8RAM；2Kx8位ROM；4Kx8ROM；8Kx8ROM，及74L138译码器和各种门电路。请画出CPU与存储器的连接图，要求：1、主存地址空间分配6000H67FFH为系统程序区6800H6BFFH为用户程序区2、合理选用上述芯片，说明各选几片？3、画出存储芯片的片选逻辑图,ECE313Fall2006,Lecture20-Memory,63/89,(1)写出对应的二进制地址码,(2)确定芯片的数量及类型,A15A14A13A11A10A7A4A3A0,ECE313Fall2006,Lecture20-Memory,64/89,(3)分配地址线,A10A0接2K8位ROM的地址线,A9A0接1K4位RAM的地址线,(4)确定片选信号,ECE313Fall2006,Lecture20-Memory,65/89,CPU与存储器的连接图,ECE313Fall2006,Lecture20-Memory,66/89,Outline-MemorySystems,OverviewMotivationGeneralStructureandTerminologyMemoryTechnologyStaticRAMDynamicRAMCacheMemory3VirtualMemory,ECE313Fall2006,Lecture20-Memory,67/89,CPU,CacheMemory,DRAMMemory,Processor,addr,data,addr,data,CacheOperation,InsertbetweenCPU,MainMem.ImplementwithfastStaticRAMHoldssomeofaprogramsdatainstructionsOperation:,ECE313Fall2006,Lecture20-Memory,68/89,FourKeyCacheQuestions:,1.Wherecanblockbeplacedincache?(blockplacement)2.Howcanblockbefoundincache?(blockidentification)3.Whichblockshouldbereplacedonamiss?(blockreplacement)4.Whathappensonawrite?(writestrategy),ECE313Fall2006,Lecture20-Memory,69/89,BasicCacheDesign,以块的方式组织块的内容标记tag-extrabitstoidentifyblock(partofblockaddress)数据data-dataorinstructionwords-contiguousmemorylocations右边的例子:每块一个字(4byte)Tag为30位Cache中有2个块,CPU,CPU,CPU,tag0,data0,CPU,CPU,tag1,data1,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,MainMemory,ECE313Fall2006,Lecture20-Memory,70/89,CacheExample(2),Assume:r1=0,r2=1,r4=21cycleforcacheaccess5cyclesformain.mem.access1cycleforinstr.executionAtcycle1-PC=0 x00FetchinstructionfrommemorylookincacheMISS-fetchfrommainmem(5cyclepenalty),CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:addr1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,MainMemory,bner4,r1,L,subr1,r1,r1,L:jL,MISS,ECE313Fall2006,Lecture20-Memory,71/89,CacheExample(3),Atcycle6Executeinstr.addr1,r1,r2,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:addr1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,MainMemory,bner4,r1,L,subr1,r1,r1,L:jL,CycleAddressOp/Instr.r1,1-5FETCH0 x000,60 x0addr1,r1,r21,ECE313Fall2006,Lecture20-Memory,72/89,CacheExample(4),Atcycle6-PC=0 x04FetchinstructionfrommemorylookincacheMISS-fetchfrommainmem(5cyclepenalty),CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:addr1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,MainMemory,bner4,r1,L,subr1,r1,r1,L:jL,CycleAddressOp/Instr.r1,1-5FETCH0 x0,60 x0addr1,r1,r21,MISS,6-10FETCH0 x4,ECE313Fall2006,Lecture20-Memory,73/89,CacheExample(5),Atcycle11Executeinstr.bner4,r1,L,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:addr1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,MainMemory,bner4,r1,L,subr1,r1,r1,L:jL,CycleAddressOp/Instr.r1,1-5FETCH0 x000,60 x0addr1,r1,r21,6-10FETCH0 x004,110 x4bner4,r1,L1,ECE313Fall2006,Lecture20-Memory,74/89,CacheExample(6),Atcycle11-PC=0 x00FetchinstructionfrommemoryHIT-instructionincache,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:addr1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,MainMemory,bner4,r1,L,subr1,r1,r1,L:jL,CycleAddressOp/Instr.r1,1-5FETCH0 x0,60 x0addr1,r1,r21,6-10FETCH0 x4,HIT,110 x4bner4,r1,L1,11FETCH0 x01,ECE313Fall2006,Lecture20-Memory,75/89,CacheExample(7),Atcycle12Executeaddr1,r1,2,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:addr1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,MainMemory,bner4,r1,L,subr1,r1,r1,L:jL,CycleAddressOp/Instr.r1,1-5FETCH0 x0,60 x0addr1,r1,r21,6-10FETCH0 x4,110 x4bner4,r1,L1,12FETCH0 x01,12addr1,r1,22,ECE313Fall2006,Lecture20-Memory,76/89,CacheExample(8),Atcycle12-PC=0 x04FetchinstructionfrommemoryHIT-instructionincache,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:addr1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,MainMemory,bner4,r1,L,subr1,r1,r1,L:jL,CycleAddressOp/Instr.r1,1-5FETCH0 x0,60 x0addr1,r1,r21,6-10FETCH0 x4,110 x4bner4,r1,L1,12FETCH0 x01,12addr1,r1,22,12FETCH0 x04,HIT,ECE313Fall2006,Lecture20-Memory,77/89,CacheExample(9),Atcycle13Executeinstr.bner4,r1,LBranchnottaken,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:addr1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,MainMemory,bner4,r1,L,subr1,r1,r1,L:jL,CycleAddressOp/Instr.r1,1-5FETCH0 x0,60 x0addr1,r1,r21,6-10FETCH0 x4,110 x4bner4,r1,L1,12FETCH0 x01,12addr1,r1,22,12FETCH0 x04,13bner4,r1,L,ECE313Fall2006,Lecture20-Memory,78/89,CacheExample(10),Atcycle13-PC=0 x08FetchInstructionfromMemoryMISS-notincache,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:addr1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,MainMemory,bner4,r1,L,subr1,r1,r1,L:jL,CycleAddressOp/Instr.r1,1-5FETCH0 x0,60 x0addr1,r1,r21,6-10FETCH0 x4,110 x4bner4,r1,L1,12FETCH0 x01,12addr1,r1,22,12FETCH0 x04,13bner4,r1,L,13FETCH0 x08,MISS,ECE313Fall2006,Lecture20-Memory,79/89,CacheExample(11),Atcycle17-PC=0 x08PutinstructionintocacheReplaceexistinginstruction,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:addr1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,MainMemory,bner4,r1,L,subr1,r1,r1,L:jL,CycleAddressOp/Instr.r1,1-5FETCH0 x0,60 x0addr1,r1,r21,6-10FETCH0 x4,110 x4bner4,r1,L1,12FETCH0 x01,12addr1,r1,22,12FETCH0 x04,13bner4,r1,L,13-17FETCH0 x08,ECE313Fall2006,Lecture20-Memory,80/89,CacheExample(12),Atcycle18Executesubr1,r1,r1,CPU,CPU,CPU,(empty),(empty),L:addr1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,MainMemory,bner4,r1,L,subr1,r1,r1,L:jL,CycleAddressOp/Instr.r1,1-5FETCH0 x0,60 x0addr1,r1,r21,6-10FETCH0 x4,110 x4bner4,r1,L1,12FETCH0 x01,12addr1,r1,22,12FETCH0 x042,13bner4,r1,L2,13-17FETCH0 x082,18subr1,r1,r10,ECE313Fall2006,Lecture20-Memory,81/89,CacheExample(13),Atcycle18FetchinstructionfrommemoryMISS-notincache,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:addr1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,MainMemory,bner4,r1,L,subr1,r1,r1,L:jL,CycleAddressOp/Instr.r1,1-5FETCH0 x0,60 x0addr1,r1,r21,6-10FETCH0 x4,110 x4bner4,r1,L1,12FETCH0 x01,12addr1,r1,22,12FETCH0 x042,13bner4,r1,L2,13-17FETCH0 x082,subr1,r1,r1,18subr1,r1,r10,18FETCH0 x0C,MISS,ECE313Fall2006,Lecture20-Memory,82/89,CacheExample(14),Atcycle22PutinstructionintocacheReplaceexistinginstruction,CPU,CPU,CPU,(empty),(empty),CPU,CPU,(empty),(empty),L:addr1,r1,r2,0 x00000000,0 x00000004,0 x00000008,0 x0000000C,0 x00000000,b0,b1,Cache,MainMemory,bner4,r1,L,subr1,r1,r1,L:jL,CycleAddressOp/Instr.r1,1-5FETCH0 x0,60 x0addr1,r1,r21,6-10FETCH0 x4,110 x4bner4,r1,L1,12FETCH0 x01,12addr1,r1,22,12FETCH0 x042,13bner4,r1,L2,13-17FETCH0 x082,18subr1,r1,r10,18-22FETCH0 x0C,ECE313Fall2006,Lecture20-Memory,83/89,CacheExample(15),CycleAddressOp/Instr.r1,1-5FETCH0 x0,60 x0addr1,r1,r21,6-10FETCH0 x4,110 x4bner3,r1,L,11FETCH0 x0,120 x8addr1,r1,22,12FETCH0 x4,130 x4bner4,