集成电路分析与设计ppt课件

集成电路分析与设计,第1讲认识集成电路设计及其设计过程,1,集成电路分析与设计课程主要介绍什么内容?,CMOS数字集成电路(CMOSdigitalIC)IC的发展历史及现状(HistoryofIC)IC设计流程和方法(DesignprocessandMethodology)IC制造工艺技术(Fabricationprocess)ICEDA（CAD）工具使用(EDAtools)CMOS反相器设计(CMOSInverter)CMOS组合逻辑门设计(CombinationalLogicCircuit)CMOS时序逻辑电路设计(SequentialLogicCircuit)IC版图设计(Layout)IC仿真技术(Simulation)存储器电路设计介绍(MemoryCircuits)模拟IC设计介绍(AnalogIC),2,集成电路分析与设计课程信息,课程性质：是一门专业基础课程主要介绍CMOS数字集成电路设计的基础知识共40课时（32理论课时+8实验课时）完成4个实验对准备从事IC行业的学生来讲，本课程只是一个基础，还需要继续深入学习更多关于IC设计的知识，如数字IC深入，模拟IC，RFIC等。,3,实验内容（共8学时）,实验一（2学时）反相器电路设计（SimulationandLayout）实验二（2学时）NAND电路设计（SimulationandLayout）实验三（2学时）AND电路设计（SimulationandLayout）实验四（2学时）D触发器电路设计（SimulationandLayout）,4,Project（选作内容）,完成一个44SRAM芯片的设计3人一组项目过程：A期中OralpresentationB期末OralpresentationC项目报告书一份D3人项目成绩相同,5,GradingPolicy,课堂提问和作业10%实验20%考试（开卷）70%规则：（1）1个问题和4次作业，每次/个2分，共10分；（2）每个实验完成得5分，共20分；（3）点名1次不到，10分没了；（4）抄作业，抄实验报告，相应分数没了；（5）请假规则：必须有正规请假手续和课前请假。,6,本课程推荐书目,教材中文版周润德等译，数字集成电路设计透视第二版，电子工业出版社(JanM.Rabaey,etal.DigitalIntegratedCircuits,2nde,PrenticeHall,2004)参考书Sung-Mo(Steve)Kang,YusufLeblebici,CMOSDigitalIntegratedCircuitsAnalysislowerpowerconsuption;morereliable.Integrationreducesmanufacturingcost（降低成本）BOM(BoardofMaterials)costreducesMassICproductionreducescost,11,ElectronicsIndustry,Design,fab,applicationEducationSoftwareCommunication/NetworkingFabcost:$2-$3billionDrivingforceofworldeconomyLargeinvestment:fab,packaging,design,EDA,Pentium4“Northwood”55Mtransistors/2-2.5GHzL=0.13m,12,MooresLaw(1965),GordonMooreIntelFounder“Thenumberoftransistorsonachipdoubledevery18to24months.”,Electronics,April19,1965.,GordonMooreIntelCo-FounderandChairmainEmeritusImagesource:IntelC,13,InformationRevolution,Electronicsystemincars.Electronicfinancialsystem:e-banking,e-money,e-stock,RFIDlablePersonalcomputing/entertainmentMedicalelectronicsystems.Internet:routers,firewalls,servers,storagesElectroniclibrary(Google,.)DVDR/W,HDTV,InteractiveTVIngeneral,consumerelectronicsetc.,14,ChallengesofICDesign,Complexity:Multi-milliontransistorsonasinglechip(smallersize/fasterspeed)Multipleandconflictingspecificationsforhighperformance(power/speed/throughput)Competition:ShortdesigntimeDesignTools:Multipletoolsinvolved,Complexdesignflow,15,RelatedtoICJobs,LayoutdesignersCircuitdesigners(Digital/Analog/RF)ArchitectsTest/VerificationengineersFabricationengineersSystemdesigners(SoC)CADtoolprogrammersEmbeddedSystemdevelopersSoftwareprogrammers,16,17,TheTransistorRevolution,FirsttransistorBellLabs,1947,J.Bardeen,W.Shockley,andW.Brattain(1956NobelprizeLaureate),18,1958年J.Kilby（TI）研制成功第一个集成电路1959年R.Noyce（Fairchild）第一个利用平面工艺制成集成电路,TheFirstIntegratedCircuits,19,TheFirstIntegratedCircuits,Bipolarlogic1960s,ECL3-inputGateMotorola1966,FirstcommercialIClogicgatesFairchild1960TTL1962intothe1990sECL1974intothe1980s,20,Intel4004Micro-Processor,19702300transistors1MHzoperation,21,IntelPentium(IV)microprocessor,Pentium4“Northwood”CommercialProduction:Year2001L=0.13m6MLCuLow-kFC-PGA2,22,MOSFETTechnology,MOSFETtransistor-Lilienfeld(Canada)in1925andHeil(England)in1935CMOS1960s,butplaguedwithmanufacturingproblems(usedinwatchesduetotheirpowerlimitations)PMOSin1960s(calculators)NMOSin1970s(4004,8080)forspeedCMOSin1980spreferredMOSFETtechnologybecauseofpowerbenefitsBiCMOS,Gallium-Arsenide,Silicon-GermaniumSOI,Copper-LowK,strainedsilicon,High-kgateoxide.,23,WorldwideSemiconductorRevenue,Source:ISSCC2003G.Moore“Noexponentialisforever,butforevercanbedelayed”,24,1Waferin1964vs.300mm(12”)Waferin2003,25,IBMPowerPC970(130nm)2003,1.8Ghz58M118mm2,ApplePowerG5,thefastestPCin2003,hasdualPPC970CPU,26,Twochipsyouareseeingtoday,Microprocessor,ASIC(ApplicationSpecificIC),27,State-of-theArt:LeadMicroprocessors,28,State-of-theArt:LeadMicroprocessors(uptodate),Pentium4180nm(2001)1.7GHz42Mtransistors217mm2Pentium4130nm(2003)3.2GHz55MTransistors131mm2Pentium490nm(2004)3.4Hz125MTransistors112mm2Pentiumon65nm(2005/2006)250MillionPentiumon45nm(2007)400to500Million,(Alluse0.13umtechnologyexceptPentium4Prescott,whichuses90nmtech),29,State-of-theArt:LeadMicroprocessors(uptodate),300mmwaferandPentium4IC.PhotoscourtesyofIntel.,30,WhatADigitalDesignerNeedstoKnow.,“MicroscopicProblems”Ultra-highspeeddesignInterconnectNoise,CrosstalkReliability,ManufacturabilityPowerDissipationClockdistribution.,“MacroscopicIssues”Time-to-MarketMillionsofGatesHigh-LevelAbstractionsReuse&IPAvailabilitysystemsonachip(SoC)Predictabilityetc.,31,32,33,34,35,36,37,38,95%,39,如何设计一个集成电路？,40,41,TheVLSIdesignprocess,工程的艺术,Maybepartoflargerproductdesign.Majorlevelsofabstraction:specificationarchitecturelogicdesigncircuitdesignlayoutdesign,42,MajorSegmentsofICIndustry,FablessDesignHouses,EDAToolsCompanies,DesignServiceCompanies,Library&IPProviders,DedicatedICManufacturers(Foundry),Post:EDA:ElectronicDesignAutomationIP:siliconIntellectualPropertyIDM:IntegratedDeviceManufacturer,Integratedservice,Packaging&TestingHouses,43,ASICDesignStyles,FullCustomDesignFlowCircuitiscreatedbycomposingatransistornetlistSPICEsimulationisperformedtoverifythecircuitKnownas“capture-and-simulate”paradigmLayoutismostlydonemanuallyPopularforhigh-performancemicroprocessors&memoriesCell-BasedSynthesisFlowDesignisfirstdescribedbyHardwareDescriptionLanguage(e.g.,VerilogandVHDL)Basedonacelllibrary,netlistiscreatedbysynthesistoolsKnownas“describe-and-synthesize”paradigmLayoutcanbedonethroughautomatictools,44,DetailedCustomDesignFlow,BlockSpecification(FiniteStateMachine,ArithmeticExpression,BooleanExpression),LogicDesign,Gate-LevelNetlist,TransistorNetlist,TechnologyMapping,SPICESimulation,SPICEModel,LayoutDesign,Layout,LayoutRules,DesignRuleChecking(DRC)Layoutvs.SchematicCheck(LVS),Parasitic(orwiring)RCextraction,Post-LayoutSPICESimulation,CheckifSPECismet?Ifyes,done.Otherwise,gobacktooptimizethedesign,45,ASimpleExample,FunctionalityOne-bitbinaryfull-adderTechnology1mmn-wellCMOStechnologySpeedInputtooutputdelay5nsArea3000mm2PowerDissipation1mWat5voltsand200MHz,Full-adder,A,B,Sum,Carry_out,C,46,LogicDesign,Logicminimizationtrick:Thecarry_outsignalisusedtorealizethefunctionofsignalsuminordertoreducetheoverallcircuitsize.,Todayslogicsynthesistools(suchasDesignCompiler)incorporatingsomeadvancedalgorithms,isabletoperformautomaticlogicminimization.,x=Carry_out,47,Transistor-LevelSchematic,TechnologymappingManysimpleANDORgatesaremergedintoacomplexgate(oracellinthecelllibrary)TransistoraspectratiopMOS(W/L)isusuallylargerthannMOS(W/L),e.g.,2:1,x,y,x,y,x=(AB+BC+CA)y=(A+B+C)x+ABC),48,InitialLayout,Post-layoutSPICEsimulationincludesthe“parasiticresistance&capacitance”ismoreaccuratethanthepre-layoutsimulation(pre-sim),Ratioofchannelwidths2:1,49,I/OSimulationWaveforms,PropagationtimetPHLortPLHasdefinedaboveLow-to-highpropagationtime（传播延时）tPLH=8.2ns!Gottogobacktooptimizethedesign!,50,OptimizedLayout,TransistorSizingchangestheaspectratios(W/L)ofselectedtransistorsAlargeraspectratiomayleadtoahigherspeedWireSizingisalsomorerecentlyproposed,PropagationDelay5ns!,51,FullCustomDesignExample（another),A/D,PLA,I/O,comp,RAM,52,Cell-BasedDesignFlow,Architecturedesign,System-levelintegration,layout,Noviolation,Memorymodule,Functionalmodel,Testbench,RTLcode,CellLibrary,synthesisview,RTL-synthesis(DesignC