集成电路设计-05-反相器动静态特性ppt课件

.,1,集成电路设计,第五章CMOS反相器,.,2,Outline,电路特性反相器CMOS反相器电压传输特性噪声容限传输延迟驱动大电容负载功耗及低功耗设计,.,3,5-1特性,成本复杂性和面积完整性和稳定性静态（稳态）特性性能动态（瞬态）特性能量效率能耗和功率,.,4,5-2反相器（Inverter）,CMOSInverter,.,5,TwoInverters,ConnectinMetal,Sharepowerandground,.,6,CMOS反相器基本特点,输出电源和GND噪声容限大逻辑电平与尺寸无关，可以采用最小尺寸稳态输出时，VDD或GND与输出之间总存在有限电阻的通路低输出阻抗对噪声和干扰不敏感极高的输入阻抗（inputresistance）稳态下Vdd和GND间无直流通路无静态功耗传输延迟（Propagationdelay）是负载电容和晶体管电阻的函数。,.,7,CMOSInverterFirst-OrderDCAnalysis,VOL=0VOH=VDDVM=f(Rn,Rp),.,8,CMOSInverter:TransientResponse,V,out,V,out,R,n,R,p,V,DD,V,DD,V,in,=,V,DD,V,in,=,0,(a)Low-to-high,(b)High-to-low,C,L,C,L,.,9,5-3VoltageTransferCharacteristic,NMOS+PMOS图解法,.,10,I-VNMOS,ID(A),VDS(V),X10-4,VGS=1.0V,VGS=1.5V,VGS=2.0V,VGS=2.5V,Lineardependence,NMOStransistor,0.25um,Ld=0.25um,W/L=1.5,VDD=2.5V,VT=0.4V,.,11,I-VPlot(PMOS),PMOStransistor,0.25um,Ld=0.25um,W/L=1.5,VDD=2.5V,VT=-0.4V,Allpolaritiesofallvoltagesandcurrentsarereversed,.,12,PMOSLoadLines,.,13,PMOSLoadLines,.,14,CMOSInverterLoadCharacteristics,.,15,CMOSInverterVTC,.,16,噪声容限,反映了对噪声的敏感程度；电路0，1电平允许的输入范围；越大越好；高电平噪声容限低电平噪声容限,.,17,Logiclevelmatching,Levelsatoutputofonegatemustbesufficienttodrivenextgate.,.,18,Transfercharacteristics,Transfercurveshowsstaticinput/outputrelationshipholdinputvoltage,measureoutputvoltage.,.,19,反相器噪声容限的三种求法,求法1最低输出高电平、最高输出低电平；找到对应的输入；求差；,VNL=VoffVilVNH=VihVon,Vol,Vol,max,Voh,min,Voh,Von,Vih,Voff,Vil,.,20,求法2单位增益点（斜率为1，-1）；找到对应的输入；求差；,VNL=VoffVilVNH=VihVon,Vol,Vol,max,Voh,min,Voh,Von,Vih,Voff,Vil,.,21,求法3工作中心点；Vin=VoutVgs=Vds找到对应的输入；求差；,.,22,NoiseMarginsDeterminingVIHandVIL,Vin,Vout,VOH=VDD,VM,Bydefinition,VIHandVILarewheredVout/dVin=-1(=gain),VOL=GND,Apiece-wiselinearapproximationofVTC,NMH=VDD-VIHNML=VIL-GNDApproximating:VIH=VM-VM/gVIL=VM+(VDD-VM)/gSohighgaininthetransitionregionisverydesirable,.,23,CMOSInverterVTCfromSimulation,Vin(V),Vout(V),0.25um,(W/L)p/(W/L)n=3.4(W/L)n=1.5(minsize)VDD=2.5VVM1.25V,g=-27.5VIL=1.2V,VIH=1.3VNML=NMH=1.2(actualvaluesareVIL=1.03V,VIH=1.45VNML=1.03V下降时间（falltime）,pullupoff.,.,32,Currentthroughtransistor,Transistorstartsinsaturationregion,thenmovestolinearregion.Vout增大充电电流减小。Vds减小。,.,33,Resistiveapproximation,可使用积分求解等效电阻平均值,.,34,Req求VDD/2，VDD区间的电阻平均值,.,35,Gatedelay,Delay:传输延迟VDD50%VDD50%VDDVDDTransitiontime:转换时间timerequiredforgatesoutputtoreach10%(logic0)or90%(logic1)offinalvalue.10%90%90%10%,.,36,Inverterdelaycircuit,Loadisresistor+capacitor,driverisresistor.,.,37,Inverterdelaywithtmodel,tmodel:gatedelaybasedonRCtimeconstantt.Vout(t)=VDDexp-t/(Rn+RL)CL90%(logic1)10%(logic0)tf=2.2RCL100%(logic1)50%tD=0.69RCLForpulluptime,usepullupresistance.,.,38,tmodelinverterdelay,0.5micronprocess:Rn=3.9kWCL=0.68fF延迟时间td=0.69x3.9x0.68E-15=1.8ps.上升延迟tf=2.2x3.9x0.68E-15=5.8ps.,.,39,QualityofRCapproximation,.,40,.,41,传播延迟50%平均延迟时间,tp=0.69CL(Reqn+Reqp)/2,tpLH,tpHL,VOUT=0.5VDD时,.,42,Rn1/n(VgsVt)Rn1/n导电因子n=k（W/L）k=nCoxCg=Cox*(W*L）,.,43,DelayasafunctionofVDD,.,44,等效电阻与W/L成反比；当VDDVt+VDD/2时，等效电阻与电源无关；当VDDzerodelay,CL,tp=kRWCL,RW,RW,Wunit=1,kisaconstant,equalto0.69,.,51,输出端电容构成,Cout=CFET+CLtf=2.2Rn(CFET+CL)tr=2.2Rp(CFET+CL)CFET由几何图形决定,.,52,InverterwithLoad,Load,Delay,Cint,CL,Delay=kRW(Cint+CL)=kRWCint+kRWCL=kRWCint(1+CL/Cint)=Delay(Internal)+Delay(Load),CN=Cunit,CP=2Cunit,2W,W,.,53,DelayFormula,Cint=gCginwithg1f=CL/Cgin-effectivefanoutR=Runit/W;Cint=WCunittp0=0.69RunitCunit,.,54,ApplytoInverterChain,.,55,OptimalTaperingforGivenN,DelayequationhasN-1unknowns,Cgin,2Cgin,NMinimizethedelay,findN-1partialderivativesResult:Cgin,j+1/Cgin,j=Cgin,j/Cgin,j-1Sizeofeachstageisthegeometricmeanoftwoneighborseachstagehasthesameeffectivefanout(Cout/Cin)eachstagehasthesamedelay,.,56,延迟时间及级数优化,Wheneachstageissizedbyfandhassameeff.fanoutf:,Minimumpathdelay,Effectivefanoutofeachstage:,.,57,Example,CL=8C1,In,Out,C1,CL/C1hastobeevenlydistributedacrossN=3stages:,.,58,级数优化,Foragivenload,CLandgiveninputcapacitanceCinFindoptimalsizingf,.,59,级数的近似,Cint=gCgin此时，忽略自载。,f=e=2.71828,N=lnF,.,60,OptimumEffectiveFanoutf,Optimumfforgivenprocessdefinedbyg,fopt=3.6forg=1,.,61,BufferDesign,1,1,1,1,8,64,64,64,64,4,2.8,8,16,22.6,Nftp164652818341542.815.3,.,62,5-6功耗（PowerDissipation）,Leadmicroprocessorspowercontinuestoincrease,.,63,ChipPowerDensity,Source:Borkar,DeIntel,.,64,ChipPowerDensityDistribution,PowerdensityisnotuniformlydistributedacrossthechipSiliconisnotagoodheatconductorMaxjunctiontemperatureisdeterminedbyhot-spotsImpactonpackaging,cooling,PowerMap,On-DieTemperature,.,65,PowerDissipation,Source:Borkar,DeIntel,来源：动态功耗（DynamicPowerConsumption）ChargingandDischargingCapacitors短路电流（ShortCircuitCurrents）CircuitPathbetweenSupplyRailsduringSwitching漏电流（Leakage）Leakingdiodesandtransistors,.,66,Powerconsumptioncircuit,Inputissquarewave.,.,67,i(t)=dQ/dt，i=c*dV/dt电压不能突变，栅电压的变化有延迟时间。Q=CVC大，意味着延迟时间加长影响C的因素？,P=V（C*dV/dt）=d（0.5CV2）/dtE=0.5CV2输入从0到VDD时，E=0.5CVDD2每次开关消耗能量。,.,68,动态功耗,AsinglecycleE=CL(VDD-VSS)2.Clockfrequencyf=1/t.EnergyE=CL(VDD-VSS)2.PowerE*f=fCL(VDD-VSS)2.影响因素fCLVDD,其中负载消耗1/2。,.,69,Energy/transition=CL*VDD2*P01Pdyn=（Energy/transition）*f=CL*VDD2*P01*fPdyn=CEFF*VDD2*fwhereCEFF=P01CL,Datadependent-afunctionofswitchingactivity!,.,70,Considera0.25micronchip,500MHzclock,averageloadcapof15fF/gate(fanoutof4),2.5Vsupply.DynamicPowerconsumptionpergateis?46.875uw?With1milliongates(assumingeachtransitionseveryclock)DynamicPowerofentirechip=?.46.875w?,.,71,LoweringDynamicPower,Pdyn=CLVDD2P01f,.,72,Speed-powerproduct,Power-delayproduct(PDP）SP=P/f=CV2,.,73,短路电流（ShortCircuitCurrent）,.,74,Durationandslopeoftheinputsignal,tscIpeakdeterminedbythesaturationcurrentofthePandNtransistorswhichdependontheirsizes,processtechnology,temperature,etc.strongfunctionoftheratiobetweeninputandoutputslopesafunctionofCL,Esc/transition=tscVDDIpeakP01Psc=tscVDDIpeakf01,.,75,IpeakasaFunctionofCL,Ipeak(A),time(sec),x10-10,x10-4,CL=20fF,CL=100fF,CL=500fF,.,76,ImpactofCLonPsc,Vin,Vout,CL,Vin,Vout,CL,Largecapacitiveload,Smallcapacitiveload,.,77,PscasaFunctionofRise/FallTimes,Pnormalized,tsin/tsout,VDD=3.3V,VDD=2.5V,VDD=1.5V,Whenloadcapacitanceissmall(tsin/tsout2forVDD2V)thepowerisdominatedbyPsc,W/Lp=1.125m/0.25mW/Ln=0.375m/0.25mCL=30fF,short-circuitcurrentisreducedwithlowersupplyvoltage,therise/falltimesof