联想KoleosII_t38_MB_H301维修原理图联想手机全型号维修图纸联想KoleosII_t38_SCH-H301

5 5 4 4 3 3 2 2 1 1 DD CC BB AA BSI ctrl AUD I/F 26M_WCN TSX 26M BPI, APC RF IQ UART Debug port Audio Speech TX MT6755 (SBS) MT6176 (LWG+LTG) Project : MT6755 (This pre-released schematic is for BOM cost estimation) REF_SCH TOP LEVEL JTAG ABB FEM RX Main 1 ANT MSDC 4-bit micro SD + hot-plug USB 2.0 / USB3.0 micro USB MSDC1 Charger/ SW MT6351 Class D/AB/G Receiver AU_VIN0 Camera IF Camera Modules Camera (MIPI CSI) VIB eMMC MSDC0 / eMMC 26M_BB 26M_RF 32K_BB I2C_APPM CTP controller Keypad LCD module Battery CLK Ctrl LCD IF BC1.1 I2C_1 / I2C_2 I2C RTC Less Headset (HPL, HPR, AU_VIN1) PWR THIRD-PARTY SPI PWRAP I/F AU_LOLP/N Audio I/F BC 1.1 Bucks VDVFS1 LDOs Vibrator MT6625L CONN ctrl Connectivity ANT LDOs MT6311 RXD RxD FEM RXD ANT I2C-APPM VBAT MSDC2 Pin-MUX CONN IF GPI CONN IQ CONN IF LCD (MIPI DSI) I2C_0 I2C MT6311 I2C MEMs & ALS/PS I2C_1 I2C SPI GPIOs SIM1 SIM1 SIM1 SIM2 SIM2 SIM2 Keypad MSDC1/Camera /SPI Pin-MUX JTAG EINT DPI USB2.0 / USB3.0 USB 2.0 / USB3.0 GPIOs / EINTs WLED BST BST_LX Flash FLASH LCM Gate Driver LCM_AVDD/AVEE Bucks SPK Driver I2C_0 I2C_1 I2C_3 26M_WCN This pre-released schematic is for BOM cost estimation Title SizeDocument NumberRev Date:Sheetof C 2860Tuesday, October 27, 2015 Title SizeDocument NumberRev Date:Sheetof C 2860Tuesday, October 27, 2015 Title SizeDocument NumberRev Date:Sheetof C 2860Tuesday, October 27, 2015 UnRegistered 5 5 4 4 3 3 2 2 1 1 DD CC BB AA Yes. AF driver (BU64297GWZ-TR) I2C address: 0X0C (Write:0 x18, Read:0 x19) Rear Camera - 16M 400 Kbps Budget Timing Yes. I2C-0 400 Kbps 400 Kbps CTP GT1151 I2C address: 0X5D (Write:0 xBA, Read:0 xBB) or 0 x14 (Write:0 x28, Read:0 x29) NT50358 / LCM Gate Driver I2C address: 0X3E (Write:0 x7C, Read:0 x7D) LCM Gate Driver I2C-2 I2CI2C Slave Address (7-bit mode)FunctionI2C Spec. TBD BQ25896/ SWCHR I2C address: 0X6B (Write:0 xTBC, Read:0 xTBC) SWCHR Yes. 400 Kbps RT4505 / Flash LED I2C address: 0X63 (Write:0 xC6, Read:0 xC7) Flash LED400 Kbps Rear camera (S5K2P8) I2C address: 0X10 (Write:0 x20, Read:0 x21) I2C-3 Yes. Yes. Baro Sensor MPU-6515 / A+Gyro I2C Address: 0 x68 (Write:0 xD0, Read:0 xD1) A+Gyro Sensor CM36558/ RGB+PS I2C address: 0 x51 (Write:0 x TBC, Read:0 xTBC) RGB / PS Sensor BMP280 / Baro I2C address: 0X77 (Write:0 xEE, Read:0 xEF) NFC I2C address: 0X28 (Write:0 x50, Read:0 x51) NFC 400 Kbps 400 Kbps 400 Kbps 400 Kbps YAS533 / M-Sensor I2C Address 0 x2E (Write: 0 x5C, Read: 0 x5D) M Sensor 1.2 Mbps I2C-1Front Camera - 8MYes.400 Kbps Front camera (OV8858) I2C address: 0X10 (Write:0 x20, Read:0 x21) AF driver (BU64245GWZ) I2C address: 0X0C (Write:0 x18, Read:0 x19) TBD MT6311 / 2-Phase Buck I2C address: 0X6B (Write:0 x, Read:0 x) MT6311 I2C Spec. : Standard mode (100 kbps) and Fast mode (400 kbps), Fast mode Plus (1 Mbps) and High-speed mode (3.4 Mbps)Note : I2C-APPM Title SizeDocument NumberRev Date:Sheetof C 2960Tuesday, October 27, 2015 Title SizeDocument NumberRev Date:Sheetof C 2960Tuesday, October 27, 2015 Title SizeDocument NumberRev Date:Sheetof C 2960Tuesday, October 27, 2015 UnRegistered 5 5 4 4 3 3 2 2 1 1 DD CC BB AA 4 mil GND trace with good shielding to PMIC (Differential) Schematic design notice of 10_BB_POWER page. Note 10-1: Connect AVDD33_USB_P1 (C32 ball) to VSIM1_PMU for IC-USB / Samrt card application. Note 10-6: Connect AVDD33_USB_P1 (C32 ball) to VUSB33_PMU for USB application. Note 10-7: AVDD28_DAC (AN6 ball) must be powered by VTCXO28_PMU. Differential pair of DVFS1 remote sense must be close to BBs ball. Remote sense trace with GNDshielding to PMIC (Differential) Note 10-2: VCORE_AO remote sense must be close to BBs ball. Remote sense trace with GNDshielding to PMIC (Differential) DVDD_MD1 and DVDD_MODEM remote sense must be close to BBs ball. Note 10-3: Note 10-4: VDRAM remote sense must be close to BBs ball. Differential pair of GPU remote sense must be close to BBs ball. Note 10-5: Note: 10-5 Note: 10-3 Note: 10-3 Note: 10-2 Note: 10-1 Note: 10-7 Note: 10-6 Note: 10-4 Note 10-8: C10091 closed DVDD28_MSDC1 150mil C10092 closed DVDD18_MSDC0 150mil Note: 10-8 This pre-released schematic is for BOM cost estimation DVDD_MD1_PMIC_FB DVDD_MD1_GND DVDD_MODEM_PMIC_FB DVDD_MODEM_GND DVDD_MD_SRAM_PMIC_FB DVDD_MD_SRAM_GND VGPU_PMIC_FB DVDD_GPU_GND DVDD_DVFS_1_PMIC_FB_6311 DVDD_DVFS1_GND_6311 VCORE_AO_PMIC_FB VCORE_AO_GND DVDD_DVFS1 AVDD18_MIPIRX VGPU_PMU DVDD_MD1_PMU VIO18_PMU DVDD_MODEM_PMU VCORE_AO_PMU DVDD_SRAM_PMU DVDD_DVFS1 VTCXO28_PMU VIO18_PMU VIO18_PMU VIO18_PMU VIO18_PMU VIO18_PMU VEFUSE_PMU VIO18_PMU VSIM1_PMU VSIM2_PMU VIO18_PMU VMC_PMU VIO18_PMU VIO18_PMU VUSB33_PMU VIO18_PMU VSIM1_PMU VUSB10_PMU VIO18_PMU VDRAM_PMU DVDD_MD_SRAM_PMU VIO18_PMU DVDD_MD1_PMU DVDD_MODEM_PMU DVDD_MD_SRAM_PMU VGPU_PMU DVDD_DVFS1 VCORE_AO_PMU DVDD_DVFS17 Title SizeDocument NumberRev Date:Sheetof D 160Tuesday, October 27, 2015 Title SizeDocument NumberRev Date:Sheetof D 160Tuesday, October 27, 2015 Title SizeDocument NumberRev Date:Sheetof D 160Tuesday, October 27, 2015 C158 1UF C1941UF C1601UF C1231UF C1591UF C1131UF C191 1UF C1531UF C116 2.2UF C173 100NF C14647UF MT6755-SBS AVDD & MD_AGND PLL PERI_D PERI_A U101F MT6755VC_M AVDD18_MDPLLGP AB20 AVDD18_MD AL22 AVDD28_DAC AN6 DVDD18_IOBL AN23 DVDD18_IOLB AH32 AVDD18_DDR F14 AVSS18_DDR E14 DVDD28_MSDC1 Y31 AVDD18_MIPIRX1 R1 AVSS18_MIPIRX1 T6 AVDD18_USB E31 DVDD28_SIM1 AA31 DVDD28_SIM2 AB32 AVSS18_MIPITX2 H31 AVSS33_USB1 E29 AVDD18_WBG N2 AVSS18_WBG4 D2 AVSS18_WBG7 E3 AVSS18_WBG6 F3 AVSS18_WBG8 F4 AVSS18_MD4 AF10 AVSS18_MD1 AF11 AVSS18_MD3 AF12 DVDD18_IOLT N32 AVDD33_USB_P0 C31 AVSS18_WBG9 G3 DVDD18_MC1 W31 AVSS18_MIPITX1 P27 DVDD18_SIM AA32 AVSS18_MD2 AF13 AVSS18_MDPLLGP AB19 AVSS18_WBG10 G4 DVSS M19 AVSS18_WBG3 H3 AVSS18_WBG5 H4 AVDD18_MIPIRX0 P2 DVDD18_IOBR AN3 AVDD18_AP AM22 DVDD18_IORB AG1 AVDD18_MIPITX H32 AVDD33_USB_P1 C32 DVDD18_IORT2 C1 DVDD18_MSDC0 B31 AVSS18_WBG1 H7 AVSS18_WBG11 J4 DVDD18_IORT1 P1 AVSS18_MD5 AF14 AVSS18_MD6 AF15 AVSS18_MD7 AF9 AVSS18_MD8 AG10 AVSS18_MD9 AG11 AVSS18_MD10 AG12 AVSS18_MD11 AG13 AVSS18_MD12 AG14 AVSS18_MD13 AG15 AVSS18_MD14 AG9 AVSS18_MD15 AH10 AVSS18_MD16 AH11 AVSS18_MD17 AH12 AVSS18_MD18 AH13 AVSS18_MD19 AH14 AVSS18_MD20 AH15 AVSS18_MD21 AH9 AVSS18_MD22 AK11 AVSS18_MD23 AK14 AVSS18_MD24 AK16 AVSS18_MD25 AK20 AVSS18_MD26 AK21 AVSS18_MD27 AL10 AVSS18_MD28 AL11 AVSS18_MD29 AL13 AVSS18_MD30 AL14 AVSS18_MD31 AL16 AVSS18_MD32 AL17 AVSS18_MD33 AL19 AVSS18_MD34 AL6 AVSS18_MD35 AL7 AVSS18_MD36 AL9 AVSS18_MD37 AM11 AVSS18_MD38 AM14 AVSS18_MD39 AM15 AVSS18_MD40 AM18 AVSS18_MD41 AM6 AVSS18_WBG12 K3 AVSS33_USB2 F30 AVSS33_USB3 G29 AVDD10_SSUSB G32 AVDD18_SSUSB F31 DVDD_VQPS B30 DVSS M20 DVSS M21 DVSS M22 DVSS M23 DVSS M24 DVSS M25 DVSS M26 DVSS M9 DVSS N10 DVSS N14 DVSS N15 DVSS N18 DVSS N19 DVSS N20 DVSS N21 DVSS N9 DVSS P10 DVSS P14 DVSS P15 DVSS P6 DVSS P9 DVSS R10 DVSS R14 DVSS R15 DVSS R22 DVSS R24 DVSS R6 DVSS R9 DVSS T10 DVSS T14 DVSS T15 DVSS T18 DVSS T19 DVSS T20 DVSS T21 DVSS T22 DVSS T23 DVSS T24 DVSS T25 DVSS T26 DVSS T27 DVSS T9 DVSS U10 DVSS U13 DVSS U14 DVSS U15 DVSS U18 DVSS U19 DVSS U20 DVSS U21 DVSS U22 DVSS U23 DVSS U24 DVSS U25 DVSS U26 DVSS U27 DVSS U9 DVSS V10 DVSS V14 DVSS V15 DVSS V18 DVSS V19 DVSS V21 DVSS V9 DVSS W10 DVSS W14 DVSS W15 DVSS W18 DVSS W19 DVSS W21 DVSS W9 DVSS Y10 DVSS Y13 DVSS Y14 DVSS Y15 DVSS Y18 DVSS Y19 DVSS Y21 DVSS Y22 DVSS Y23 DVSS Y24 DVSS Y25 DVSS Y26 AVSS18_WBG2 L3 AVSS10_SSUSB H30 AVSS18_MIPIRX2 U6 AVSS18_MIPIRX3 V6 AVSS18_MIPIRX4 W6 AVSS18_WBG13 M2 DVSS Y27 DVSS Y30 AVSS18_WBG14 M3 DVSS Y6 DVSS Y9 AVSS18_MD42 AN19 DVSS G8 DVSS F8 DVSS E13 DVSS D16 DVSS AA17 DVSS AA16 C14222UF C1241UF C184 100NF C106 470nF C1434.7uF C15547UF C168470nF C182 100NF C14922UF C1631UF C13647UF C109 10UF C196 100NF C1191UF C185 100NF MD1GPU MT6755-SBS DVFS VCCK MODEM SRAM VDDQ SRAM U101E MT6755VC_M DVDD_MFG1 J22 DVDD_DVFS3 AB22 DVDD_DVFS32 AB23 DVDD_MFG2 J23 DVDD_MFG3 J24 DVDD_MFG6 J25 DVDD_MFG9 J26 DVDD_MFG10 J27 DVDD_DVFS2 AB24 DVDD_DVFS4 AB25 DVDD_DVFS5 AB26 DVDD_DVFS6 AB27 DVDD_DVFS7 AC22 DVDD_DVFS8 AC23 DVDD_DVFS9 AC24 DVDD_DVFS10 AC25 DVDD_DVFS11 AC26 DVDD_DVFS12 AC27 DVDD_DVFS13 AC28 DVDD_DVFS14 AC32 DVDD_DVFS15 AD28 DVDD_DVFS16 AD29 DVDD_DVFS17 AD30 DVDD_DVFS18 AD31 DVDD_DVFS19 AD32 DVDD_DVFS20 AE28 DVDD_DVFS21 AF21 DVDD_DVFS22 AF22 DVDD_DVFS23 AF23 DVDD_DVFS24 AF24 DDRV1 E18 DDRV6 F12 DDRV7 F15 DDRV8 F18 DDRV9 F22 DDRV10 F19 DVDD_DVFS25 AF25 DVDD_DVFS26 AF26 DVDD_DVFS27 AF27 DVDD_DVFS28 AG21 DVDD_DVFS29 AG22 DVDD_MODEM3 AA11 DVDD_MODEM4 AA12 DVDD_MODEM5 AA7 DVDD_MODEM6 AA8 DVDD_MODEM7 AB11 DVDD_MODEM8 AB12 DVDD_MODEM9 AB7 DVDD_MODEM12 AB8 DVDD_MODEM13 AC11 DVDD_MODEM14 AC7 DVDD_MODEM15 AC8 DVDD_MODEM16 AD11 DVDD_MODEM17 AD12 DVDD_MODEM18 AD7 DVDD_MODEM19 AD8 DVDD_MODEM20 AE11 DVDD_DVFS30 AG23 DVDD_DVFS31 AG24 DDRV11 F9 DVDD_MODEM22 AE7 DVDD_MODEM23 AE8 DVDD_MODEM24 AF7 DVDD_MODEM25 AF8 DVDD_MODEM26 AG7 DVDD_MODEM27 AG8 DVDD_MODEM28 L11 DVDD_MODEM29 L7 DVDD_MODEM30 L8 DVDD_MODEM31 M11 DVDD_MFG4 K22 DVDD_MFG5 K23 DVDD_MFG7 K24 DVDD_MFG8 K25 DVDD_MODEM11 M7 DVDD_MFG12 K26 DVDD_MFG11 K27 DVDD_MODEM10 M8 DVDD_SRAM_MODEM2 AC12 DDRV_CLK G9 DVDD_MODEM21 N11 DVDD_MODEM32 N7 DVDD_MFG13 N22 DVDD_MFG14 N23 DVDD_MFG15 N24 DVDD_SRAM_MODEM1 AE12 DVDD_DVFS33 AG25 DVDD_DVFS34 AG26 DVDD_DVFS35 AG27 DVDD_DVFS36 V22 DVDD_DVFS37 V23 DVDD_DVFS38 V24 DVDD_DVFS39 V25 DVDD_SRAM1 AB21 DVDD_SRAM2 AC21 DVDD_SRAM_MODEM3 L12 DVDD_SRAM_MODEM4 P12 DVDD_SRAM_MODEM5 U12 DVDD_MODEM33 N8 DVDD_MODEM34 P11 DVDD_TOP2 AD16 DVDD_TOP3 AD17 DVDD_TOP4 AD18 DVDD_TOP5 AD19 DVDD_TOP6 AD20 DVDD_TOP7 AG16 DVDD_TOP8 AG17 DVDD_TOP9 AG18 DVDD_TOP10 AG19 DVDD_TOP11 AG20 DVDD_TOP12 J11 DVDD_TOP13 J17 DVDD_TOP14 J19 DVDD_TOP15 J21 DVDD_TOP16 J7 DVDD_TOP17 J9 DVDD_TOP18 K10 DVDD_TOP19 K11 DVDD_TOP20 K12 DVDD_TOP21 K13 DVDD_TOP22 K14 DVDD_TOP23 K15 DVDD_TOP24 K16 DVDD_TOP25 K17 DVDD_TOP26 K19 DVDD_TOP27 K21 DVDD_TOP28 K7 DVDD_TOP29 K8 DVDD_TOP30 K9 DVDD_TOP31 L18 DVDD_TOP32 L19 DVDD_TOP33 L20 DVDD_TOP34 L21 DVDD_TOP35 P18 DVDD_TOP36 P19 DVDD_TOP37 P20 DVDD_TOP38 P21 DVDD_TOP39 R18 DVDD_TOP40 R19 DVDD_TOP41 R20 DVDD_DVFS40 V26 DVDD_DVFS41 V27 DVDD_DVFS42 W22 DVDD_MFG16 N25 DVDD_MFG17 N26 DVDD_MFG18 P22 DVDD_MFG19 P23 DVDD_MFG20 P24 DVDD_MFG21 P25 DVDD_MFG22 P26 DVDD_DVFS43 W23 DVDD_DVFS44 W24 DVDD_DVFS45 W25 DVDD_DVFS46 W26 DVDD_SRAM_MODEM6 Y12 DVDD_TOP1 R21 DVDD_MODEM35 P7 DVDD_MODEM36 P8 DVDD_MODEM37 R11 DVDD_MODEM38 R7 DVDD_MODEM39 R8 DVDD_MODEM40 T11 DVDD_MODEM41 T12 DVDD_MODEM42 T7 DVDD_MODEM43 T8 DVDD_MODEM44 U11 DVDD_MODEM45 U7 DVDD_MODEM46 U8 DVDD_MODEM47 V11 DVDD_MODEM48 V12 DVDD_MODEM49 V8 DVDD_MODEM50 W11 DVDD_MODEM51 W12 DVDD_MODEM52 W7 DVDD_MODEM53 W8 DVDD_MODEM54 Y11 DVDD_MODEM2 Y7 DVDD_MODEM1 Y8 DVDD_DVFS1 W27 DVDD_SRAM_MODEM_1_4 AC16 DDRV12 G15 DDRV2 F10 DDRV3 F16 DDRV4 G10 DDRV5 G12 DDRV13 G16 DDRV14 G19 DDRV15 G22 DDRV16 G23 DVDD_MFG23 H27 DVDD_MFG24 R23 DVDD_MFG25 R25 DVDD_MFG26 R26 DVDD_MFG27 R27 DVDD_SRAM_MODEM_1_1 AB16 DVDD_SRAM_MODEM_1_2 AB17 DVDD_SRAM_MODEM_1_3 AC17 DVDD_MD1_17 P16 DVDD_MD1_38 Y20 DVDD_MD1_18 P17 DVDD_MD1_1 AA13 DVDD_MD1_37 Y17 DVDD_MD1_2 AA20 DVDD_MD1_19 R12 DVDD_MD1_36 Y16 DVDD_MD1_3 AB13 DVDD_MD1_20 R13 DVDD_MD1_35 U16 DVDD_MD1_21 R16 DVDD_MD1_4 AD13 DVDD_MD1_22 R17 DVDD_MD1_34 W17 DVDD_MD1_5 L13 DVDD_MD1_33 W16 DVDD_MD1_6 L16 DVDD_MD1_7 L17 DVDD_MD1_32 W13 DVDD_MD1_31 V20 DVDD_MD1_8 M12 DVDD_MD1_30 V17 DVDD_MD1_9 M13 DVDD_MD1_10 M16 DVDD_MD1_29 V16 DVDD_MD1_28 W20 DVDD_MD1_11 M17 DVDD_MD1_12 N12 DVDD_MD1_27 V13 DVDD_MD1_26 U17 DVDD_MD1_13 N13 DVDD_MD1_14 N16 DVDD_MD1_25 T17 DVDD_MD1_24 T16 DVDD_MD1_15 N17 DVDD_MD1_16 P13 DVDD_MD1_23 T13 C107 470nF C183100NF C114 100NF N.M. C169470nF C164 1UF C172 100NF C1331UF C14047UF C1311UF C139 100NF C112 470nF C193 1UF C1054.7uF C170470nF C1151UF C1251UF C117 1UF C187 100NF C198 4.7uF C174 10UF C147 470nF C190 100NF C199 100NF C171470nF C1414.7uF C151 1UF C1521UF C1111UF C1791UF C177 100NF C176 100NF C102470nF C138 47UF C1541UF C1444.7uF C175 4.7uF C101470nF C188 100NF C150 1UF C186 100NF C103470nF C192 100NF C1611UF C145 4.7uF C180 100NF C126 22UF C1181UF C195 1UF C178 1UF C189 100NF C197 100NF C100 1UF C148 2.2UF C104470nF C162 1UF C181 100NF C1101UF UnRegistered 5 5 4 4 3 3 2 2 1 1 DD CC BB AA Schematic design notice of 11_BB_1 page. Note 11-1: PWRAP_SPI0_CSN and AUD_DAT_MOSI are JTAG feature in bootstrap. Note: 11-2 Note 11-2: The de-coupling cap. of DRAM VREF have to be placed as close to BB as possible. PWRAP_SPI0_CSNAUD_DAT_MOSIJTAG HILO HIHI LO LO LOHI N/A SPI_CSB/SPI_CLK/SPI_MO/SPI_MI CAM_PDN0/CAM_PDN1/CAM_RST0/CAM_RST1 MSDC1_CLK/MSDC1_CMD/MSDC1_DAT0/MSDC1_DAT1 Note: 11-2 Note: 11-1 Close to AP IC. This pre-released schematic is for BOM cost estimation R205&R206共焊盘共焊盘 AUD_DAT_MOSI_1 PWRAP_SPI0_CSN PWRAP_SPI0_CSN AUD_DAT_MOSI_1 VREF_AP EXTDN X26M_IN LTE_RX_REF AUX_IN0_NTC AUX_IN1_NTC REFP CURRENT_ADC PWRAP_SPI0_MO VIO18_PMU VIO18_PMU VDRAM_PMU WATCHDOG5,7 SRCLKENA05,21 SRCLKENA15,21 SYSRSTB5 RTC32K1V85 PWRAP_SPI0_CSN5 PWRAP_SPI0_CK5 PWRAP_SPI0_MO5 PWRAP_SPI0_MI5 EVREF2,8 EVREF2,8 SIM1_SRST12 SIM1_SCLK12 SIM1_SIO12 SIM2_SRST12 SIM2_SCLK12 SIM2_SIO12 LTE_BSI_CK21 LTE_BSI_EN21 LTE_BSI_D221 LTE_BSI_D121 LTE_BSI_D021 MIPI0_SCLK22 MIPI0_SDATA22 RFIC_CLK_BB21 LTE_TX_BB_IP21 LTE_TX_BB_IN21 LTE_TX_BB_QP21 LTE_TX_BB_QN21 APC124 LTE_PRX_BB1_IP21 LTE_PRX_BB1_IN21 LTE_PRX_BB1_QP21 LTE_PRX_BB1_QN21 LTE_DRX_BB1_QP21 LTE_DRX_BB1_QN21 LTE_DRX_BB1_IP21 LTE_DRX_BB1_IN21 LTE_PRX_BB2_IP21 LTE_PRX_BB2_IN21 LTE_PRX_BB2_QP21 LTE_PRX_BB2_QN21 LTE_DRX_BB2_IP21 LTE_DRX_BB2_IN21 LTE_DRX_BB2_QP21 LTE_DRX_BB2_QN21 LTE_DET_BB_QP21 LTE_DET_BB_QN21 LTE_DET_BB_IP21 LTE_DET_BB_IN21 AUX_IN0_NTC13 AUX_IN1_NTC22 MIPI1_SDATA24,26 MIPI1_SCLK24,26 CURRENT_ADC6 BAT_ID6 I2S1_LRCK_828116 I2S1_BCK_828116 I2S1_DOUT_828116 FP_INT15 FP_ID15 FP_SLEEP15 I2S2_DIN_828116 I2S0_BCK_828116 I2S0_LRCK_828116 BPI_BUS3_DIV_SW125 BPI_BUS4_DIV_SW225 BPI_BUS5_DIV_SW325 CHARGEOK6 BPI_BUS10_ANT_INT26 8281_CODEC_1V8_EN16 CLK1_BB5 ACCEL_GYRO_INT213 ACCEL_GYRO_INT113 EINT2_828116 AUX_IN2_NTC22 Finger_VCC_EN13 Title SizeDocument NumberRev Date:Sheetof C 260Tuesday, October 27, 2015 Title SizeDocument NumberRev Date:Sheetof C 260Tuesday, October 27, 2015 Title SizeDocument NumberRev Date:Sheetof C 260Tuesday, October 27, 2015 C201 1UF C204 1UF RFI_C MT6755-SBS SIM BPI ABB_IF RF MIPI AUX IN REF POWER U101B MT6755VC_M SIM1_SCLK AC29 SIM1_SIO AB31 SIM1_SRST AB30 SIM2_SCLK AB29 SIM2_SIO AA30 SIM2_SRST AA29 TX_SWAP1 AL2 TX_SWAP0 AL3 BPI_BUS11 AJ26 BPI_BUS10 AJ25 TX_SWAP2 AM2 BPI_BUS8 AL26 BPI_BUS7 AN26 BPI_BUS6 AL27 BPI_BUS5 AM27 BPI_BUS4 AN27 BPI_BUS3 AN5 BPI_BUS2 AM5 BPI_BUS1 AM4 BPI_BUS0 AM3 RFIC0_BSI_CK AL23 RFIC0_BSI_D2 AN24 RFIC0_BSI_D1 AK24 RFIC0_BSI_D0 AK23 BPI_ANT3 AN29 BPI_ANT2 AM29 BPI_ANT1 AM28 BPI_ANT0 AL28 DET_BPI1 AL4 DET_BPI0 AK4 TX_SWAP3 AK2 MISC_BSI_DO_0 AL25 MISC_BSI_CK_0 AK25 MISC_BSI_DO_1 AM26 MISC_BSI_CK_1 AM25 DET_BBIP AK15 DET_BBIN AL15 DET_BBQP AN15 DET_BBQN AN14 REFN AN21 APC1 AL8 AUXIN2 AL20 AUXIN1 AM21 AUXIN0 AM20 MAIN_X26M_IN AH18 TX_BBIP AN11 TX_BBIN AN12 TX_BBQP AM12 TX_BBQN AM13 PRX_BB1_IP AJ9 PRX_BB1_IN AK9 PRX_BB1_QP AJ10 PRX_BB1_QN AK10 DRX_BB1_IP AM7 DRX_BB1_IN AM8 DRX_BB1_QP AN9 DRX_BB1_QN AN8 RFIC_ET_N AK13 RFIC0_BSI_EN AM24 REFP AN22 RFIC_ET_P AK12 BPI_BUS9 AK26 MISC_BSI_DO_2 AL5 MISC_BSI_CK_2 AK5 MISC_BSI_DO_3 AK7 MISC_BSI_CK_3 AK6 AUXIN3 AL21 AUXIN4 AM19 PRX_BB2_IP AN18 PRX_BB2_IN AN17 PRX_BB2_QP AM16 PRX_BB2_QN AM17 DRX_BB2_IP AK19 DRX_BB2_IN AK18 DRX_BB2_QP AJ17 DRX_BB2_QN AK17 RX_REF AM10 PA_VM1 AL1 PA_VM0 AK1 MT6755-SBS PLLs Test Pin PMU_IF DRAM_IF GND GND U101A MT6755VC_M SYSRSTB T29 WATCHDOG R29 SRCLKENA0 T31 SRCLKENA1 T32 RTC32K_CK T30 PWRAP_SPI0_CSN V28 PWRAP_SPI0_CK V30 PWRAP_SPI0_MO T28 AUD_CLK_MOSI P31 AUD_DAT_MOSI N31 AUD_DAT_MISO R31 TESTMODE P29 TP_MEMPLL H15 TN_MEMPLL H16 EXTDN C2 VREF_CA F24 VREF_DQ F25 VREF_AP E27 DDRV_VREF F23 PWRAP_SPI0_MI U28 DVSS A1 DVSS A2 DVSS A31 DVSS A32 DVSS A8 DVSS AA10 DVSS AA14 DVSS AA15 DVSS AA18 DVSS AA19 DVSS AA21 DVSS AA22 DVSS AA23 DVSS AA24 DVSS AA25 DVSS AA26 DVSS AA27 DVSS AA6 DVSS AA9 DVSS AB10 DVSS AB14 DVSS AB15 DVSS AB18 DVSS AB6 DVSS AB9 DVSS AC10 DVSS AC13 DVSS AC14 DVSS AC15 DVSS AC18 DVSS AC6 DVSS AC9 DVSS AD10 DVSS AD14 DVSS AD15 DVSS AD22 DVSS AD23 DVSS AD24 DVSS AD25 DVSS AD26 DVSS AD27 DVSS AD6 DVSS AD9 DVSS AE10 DVSS AE13 DVSS AE14 DVSS AE15 DVSS AE16 DVSS AE17 DVSS AE18 DVSS AE19 DVSS AE20 DVSS AE22 DVSS AE23 DVSS AE24 DVSS AE25 DVSS AE26 DVSS AE27 DVSS AE6 DVSS AE9 DVSS AF16 DVSS AF17 DVSS AF18 DVSS AF19 DVSS AF20 DVSS AH24 DVSS AH25 DVSS AH7 DVSS AH8 DVSS AM32 DVSS AN1 DVSS AN2 DVSS AN32 DVSS B26 DVSS C13 DVSS C14 DVSS C18 DVSS C21 DVSS C22 DVSS C25 DVSS C5 DVSS C9 DVSS D24 DVSS D25 DVSS D5 DVSS D6 DVSS D9 DVSS E10 DVSS E11 DVSS E12 DVSS E15 DVSS E16 DVSS E17 DVSS E20 DVSS E21 TP_PLLGP AC19 TN_PLLGP AC20 DVSS E22 DVSS E25 DVSS E26 DVSS E6 DVSS E7 DVSS H10 DVSS H25 DVSS H26 DVSS H8 DVSS J10 DVSS J13 DVSS J14 DVSS J18 DVSS J20 DVSS J8 DVSS K18 DVSS K20 DVSS L10 DVSS L14 DVSS L15 DVSS L22 DVSS L23 DVSS L24 DVSS L25 DVSS L26 DVSS L9 DVSS M10 DVSS M14 DVSS M15 DVSS M18 DVSS C12 DVSS D14 DVSS E23 DVSS E24 DVSS E8 DVSS E9 DVSS D10 DVSS D11 DVSS D15 C206 100NF N.M. C202 100NF N.M. R2060R C207 100NF N.M. R205NM N.M. R2034.7K R2084.7KN.M. R2044.7KN.M. R210 47K R2094.7KN.M. C205 100NF R201 240R UnRegistered 5 5 4 4 3 3 2 2 1 1 DD CC BB AA Schematic design notice of 12_BB_2 page. Note 12-1: I2C APPM is dedicated for MT6311 2-phase buck control. Place Outside shielding case CTP/CHARGE1/LCD Backlight/ LCD Bais /Psensor/Gsensor/E_compass/ CHARGE2/ FLASH DRIVER/ SMARTPA/RGB Driver Main CAM MT6311 Note: 12-1 Place Outside shielding case This pre-released schematic is for BOM cost estimation SUB camera/NFC DPI_HSYNC: I*SPI1_A_MI DPI_DE: O*SPI1_A_MO DPI_VSYNC: