DDR2 Layout 布线规则

DDR2 Layout Request1. Routing rules for CLK1) From OPL-06750-BG to 22 match resistor should be less than 30mm.2) From 22ohm match resistor to 100 diff. match resistor should be less than 135mm.3) From 100 diff. match resistor to DDR2 chip should be less than 5mm.4) Total length: 80mm CLK/CLK# 120mm1、时钟路由规则1）从opl-06750-bg 到22匹配电阻应小于30mm。2) From 22ohm match resistor to 100 diff. match resistor should be less than 135mm.2）从22ohm匹配电阻到100不同匹配电阻应小于135mm。3) From 100 diff. match resistor to DDR2 chip should be less than 5mm.3）从100不同匹配电阻到DDR2内存芯片应小于5mm。4) Total length: 80mm CLK/CLK# 120mm4）总长度：80mm 时钟/时钟#1202. Routing rule for Address/Command signals (DDR2_A0-A12/CAS/RAS/CS/WE/CKE/ODT)1) From OPL-06750-BG to 22 match resistor should be less than 70mm.2) From 22 match resistor to DDR2 chip should be less than 75mm.3) The total routing length should be less than 155mm.4) Tcmd/addr + 0.1ns= Tclk.2。地址/命令信号路由规则（ddr2_a0-a12 / CAS / RAS / CS /我们/非常/ ODT）1) From OPL-06750-BG to 22 match resistor should be less than 70mm.1）从opl-06750-bg到 22匹配电阻应小于70mm。2) From 22 match resistor to DDR2 chip should be less than 75mm.2）从22到DDR2芯片匹配电阻应小于75mm。3) The total routing length should be less than 155mm.3）的总路径长度不应超过155毫米。4) Tcmd/addr + 0.1ns= Tclk.4）TCMD /地址+ 0.1nsTCLK3. Routing rule for DQ/DM/DQS1) From OPL-06750-BG to 22ohm match resistor should be less than 40mm.2) From 22ohm match resistor to DDR2 chip should be less than 20mm.3) DQ/DM total routing length should be less than 60mm.3。路由规则的DQ / DM /的DQS1) From OPL-06750-BG to 22ohm match resistor should be less than 40mm.1）从opl-06750-bg到22ohm匹配电阻应小于40mm。2) From 22ohm match resistor to DDR2 chip should be less than 20mm.2）从22ohm 到DDR2芯片匹配电阻应小于20mm。3) DQ/DM total routing length should be less than 60mm.3）DQ / DM总路径长度应小于60mm。4) DQS/DQS#total routing length should be less than 60mm.4）DQS /的DQS #总路径长度应小于60mm。5) 140mm CK/CK# + DQS/DQS#4. Via placement rules within the byte lane(DQ,DQS,DM)1) Maximum number of Via within the same bit is 2.2) The number of Via within the same byte lane and the distance between each Via should be same.3) If there is any Via along with DQS line, the routing length difference between the differential pair should be less than 0.4mm.4) The Via clearance should be as small as possible.5) Take care not to cut the GND plane by placing the Via clearance in rows.6) Do not route any signal where GND place does not exist under the signals due the Via clearance.5. DDR2 single side trace impedance: 50 (10%); Differential traces impedance: 100 (10%).4。通过配置规则的字节通道（DQ，DQS，DM）1) Maximum number of Via within the same bit is 2.1）过孔数最多两个。2) The number of Via within the same byte lane and the distance between each Via should be same.2）在同一字节通道之间的过孔的数量要一样并且每个过孔的距离应该是一样的。（同时转层）3) If there is any Via along with DQS line, the routing length difference between the differential pair should be less than 0.4mm.3）如果有任何过孔在DQS线上，两条差分对之间的长度差应小于0.4mm。4) The Via clearance should be as small as possible.4）过孔的间隙应尽可能小。5) Take care not to cut the GND plane by placing the Via clearance in rows.5）放置过孔时不要把地平面切割。6) Do not route any signal where GND place does not exist under the signals due t