片上多核处理器架构.ppt

片上多核处理器架构,QiZhang(张琦)CS,USTCxiaogaDec.2007,2,提纲,3,片上多核处理器,IBM2001，双核RISC处理器Power42006，Cell处理器HP2004，PA-RISC8800双核处理器SUN2004，UltraSPARCIV双核处理器AMD2005，Opteron(酷龙，服务器和工作站)2005，Athlon64X2双核系列(速龙，台式机)2007，Barcelona四核(巴塞罗那)INTEL2006，Woodcrest(Xeon5100)2006，Clovertown四核,4,发展趋势,提高处理器性能提高主频更多核心主频的提高带来功耗的提高，传统的体系结构技术已面临瓶颈，纷纷转向多线程和多内核。,5,片上多核处理器体系结构,CMP(ChipMulti-Processor)将多个计算内核集成在一个处理器芯片中，从而提高计算能力同构多核Intel，AMD异构多核Cell(主处理核+协处理核),6,核间通信,硬件结构必须支持核间通信CMP处理器各核心执行的程序之间需要进行数据共享和同步高效的通信机制是CMP处理器高性能的重要保障主流片上高效通信机制基于总线共享的cache结构基于片上的互连结构,7,总线共享cache结构,每个CPU内核拥有共享的二级或三级cache(lastlevelcache)，用于保存比较常用的数据，并通过连接核心的总线进行通信。优点结构简单通信速度高缺点基于总线的结构可扩展性较差,8,基于片上互连的结构,每个CPU核心具有独立的处理单元和cache，各个核心通过交叉开关或片上网络等方式连接在一起，各个核心间通过消息通信。优点可扩展性好数据带宽有保证缺点硬件结构复杂软件改动较大,9,如何有效地利用多核技术？,现状客户端应用程序开发者多年来一直停留在单线程世界，生产“顺序软件”。多核时代到来后软件开发者必须找出新的开发软件的方法，选择程序执行模型。,10,程序执行模型,编译器设计人员与系统实现人员之间的接口编译器设计人员将一种高级语言程序按一种程序执行模型转换成一种目标机器语言程序系统实现人员该程序执行模型在具体目标机器上的有效实现程序执行模型的适用性决定多核处理器能否以最低的代价提供最高的性能,11,IntelCore微架构,12,Intel双核,13,IntelConroe,14,IntelCore微架构,15,Intel四核,16,Intel四核,17,AMD双核,18,AMD四核酷龙,LargesharedL3cachesharesdatabetweencoresefficientlywhilehelpingreducelatencytomainmemoryDedicatedL1andL2cachepercorehelpsperformanceofvirtualizedenvironmentsandlargedatabasesbyreducingcachepollutionassociatedwithasharedL2cacheTheL1cacheofAMDOpteronprocessorscanhandledoublethenumberofloadspercycleasSecond-GenerationAMDOpteronprocessorstohelpkeepCPUcoresbusy,19,Cell处理器架构,20,Tile64,21,TILE64ProcessorBlockDiagram,22,Tile64ProcessorFamily,TheTILE64familyofmulticoreprocessorsdeliversimmensecomputeperformancetodrivethelatestgenerationofembeddedapplications.Thisrevolutionaryprocessorfeatures64identicalprocessorcores(tiles)interconnectedwithTilerasiMeshon-chipnetwork.Eachtileisacompletefull-featuredprocessor,includingintegratedL1&L2cacheandanon-blockingswitchthatconnectsthetileintothemesh.Thismeansthateachtilecanindependentlyrunafulloperatingsystem,ormultipletilestakentogethercanrunamulti-processingoperatingsystemlikeSMPLinux.TheTILE64processorfamilyslashesboardrealestateandsystemcostbyintegratingacompletesetofmemoryandI/Ocontrollers,thuseliminatingtheneedforanexternalNorthBridgeorSouthBridge.Itdeliversscalableperformance,powerefficiencyandlowprocessinglatencyinanextremelycompactfootprint.WithastandardANSICprogrammingenvironment,developerscanleveragetheirexistingsoftwareinvestmentaswellasutilizethevastbodyofOpenSourcecodeavailable.Tilescanbegroupedintoclusterstoapplytheappropriateamountofhorsepowertoeachapplication.SincemultipleoperatingsysteminstancescanberunontheTILE64simultaneously,itcanreplacemultipleCPUsubsystemsforboththedataplaneandcontrolplane.,23,FeaturesofTile64,8X8gridofidentical,generalpurposeprocessorcores(tiles)3-wayVLIWpipelineforinstructionlevelparallelis