SVTB半导体资料大全SVTB

IntroductiontoSystemVerilogforTestbench,OneDayQuickStart,RobertFreemanChrisSpearCAE,TestbenchACWWAS,2/24/05,Agenda,IntroductionGettingStartedLanguageBasicsConnectingtoyourDUTDriving,Sampling,SynchronizingOOPBasicsRandomizationSpawningProcessesFunctionalCoverageTestbenchMethodology,2/24/05,Bytheendofthisclass,youshouldbeableto:,LectureObjectives,DevelopselfcheckingtestbenchesusingSystemVerilog3.1aHowtoconnectyourDesigntoaSVtestbenchHowtoperformrandomconstrainedtestingHowtotakeadvantageofpowerfulconcurrencyHowtoimplementFunctionalCoverageHowtoincorporateMethodologyconcepts,2/24/05,BasedonSystemVerilog3.1aStandardDetailedinLanguageReferenceManualVerificationspecificlanguagefeaturesSystemVerilogAssertions(SVA)CoverageBestinClassConstraintSolverThispresentationisbasedonconstructspresentlyimplementedinVCS2005.06Alpha,SystemVerilogforVerification,Introduction,2/24/05,VerificationEnvironmentDefinitions,DUT,Driver,Transactor,Monitor,SuppliesdatatotheDUT,ObservesdatafromDUT,Executestransactions,Identifiestransactions,Checkscorrectness,Createsstimulus,Testbench,Assertions,Test,Checker,SelfCheck,VerificationEnvironment,2/24/05,Agenda,IntroductionGettingStartedLanguageBasicsConnectingtoyourDUTDriving,Sampling,SynchronizingOOPBasicsRandomizationSpawningProcessesFunctionalCoverageTestbenchMethodology,2/24/05,WhatareWeGoingtoDiscuss?,GettingStarted,SetupbasicsSV3.1aTestbenchVerificationFlowCompilingandRunninginVCSDebuggingDocumentationandsupportTheProgramBlock,2/24/05,GettingStarted,Placethefollowinginyour.cshrcsetenvVCS_HOMEsetenvSNPSLMD_LICENSE_FILEporthost:porthost.setpath=($VCS_HOME/bin$path),SetupBasics,2/24/05,GettingStarted,SVTestbenchFlow,HDL,Compilation,Simulation,Compile,HDLSimulator,HDLdut.v,SingleUnixProcess,SVTestbenchProgramtest.v,2/24/05,Compile:vcs+svtbtest.vdut.v+svtbEnableSVTestbenchconstructs(Willbesveriloginfinalrelease)-debugEnabledebugexceptlinestepping-debug_allEnabledebugincludinglinesteppingRun:simv+user_tb_runtime_options-llogfileCreatelogfile-ucliRunwithnewdebugger(seenextpage)-icmd.keyExecuteUCLIcommands-kkeyfileRenamekeyfile,GettingStarted,CompilingandRunningwithVCS,SeetheVCSUserGuideforalloptions,2/24/05,GettingStartedDebugging,UCLI:UnifiedCommandLineInterfaceMakesDebugEasyandConvenientCommonlook-and-feelenvironmentacrossSNPStoolsRuntimeFeaturesUCLIacceptsbothVHDLandVerilogpathnamesTCLscriptingfriendlyLogscommandsforreplay,CommandLineDebugger,MagellanMixedHDLVHDLNTBVERA,SystemVerilogDesignSystemVerilogAssertionsSystemVerilogTestbenchCoverageCbug/SystemC,2/24/05,GettingStarted-Debugging,callCalltasks,functions,oruserPLIchangeDepositavalueonasignalorvariablecontinueContinueuntilthenextbreakpoint(assertions,userinterrupts,simulationend,$stop)editInvokesaspecifiededitorenvDisplaysanenvironmentarrayorqueryanarrayelementfinishFinishes/endsrunningaprocess/simulation,forcevariable=valueForcesavalueonavariablegetvariableDisplaysthecurrentvalueofavariablehelpDisplaysinfoonallorspecificcommandslistingDisplaynlinesofsourcecodearoundcurrentlinenextStepovertasks/clockingblock/classdeclarations/tasks/functions/variablesinitialbegin;endendprogram,GettingStarted-SV3.1aProgramBlock,SV3.1aProgramBlockStructure,Partofdesignhierarchy,likemodule,butalwaysaleaf,2/24/05,GettingStarted-SV3.1aProgramBlock,Benefits:EncapsulatesthetestbenchSeparatesthetestbenchfromtheDUTProvidesanentrypointforexecutionCreatesascopetoencapsulateprogram-widedataFunctionality:CanbeinstantiatedinanyhierarchicallocationTypicallyatthetoplevelPortscanbeconnectedinthesamemannerasanyothermoduleExecutesintheSVreactiveregion,ProgramBlock,2/24/05,GettingStartedTestbenchTiming,Thetestbench(program)runsseparatelyfromdesign(module)TriggeredbyclockSamplesjustbeforeclockedge,drivesjustafterclock,SystemVerilogTestbenchinSimulation,clock,Sampleinputs,Driveoutputs,Design,Testbench,2/24/05,Agenda,IntroductionGettingStartedLanguageBasicsConnectingtoyourDUTDriving,Sampling,SynchronizingOOPBasicsRandomizationSpawningProcessesFunctionalCoverageTestbenchMethodology,2/24/05,SVLanguageBasics,SystemVerilog3.0and3.1basicsDatatypesArraysSubroutinesAssumeyoualreadyknowmostVerilog-1995and2001constructs,WhatareWeGoingtoDiscuss?,2/24/05,BasicSystemVerilogDataTypes,regr;/4-stateVerilog-2001logicw;/4-valuedlogic,seebelowbitb;/2-statebit0or1integeri;/4-state,32-bits,signedVerilog-2001byteb8;/8bitsignedintegerinti;/2-state,32-bitsignedintegershortints;/2-state,16-bitsignedintegerlongintl;/2-state,64-bitsignedinteger,Explicit2-statevariablesallowcompileroptimizationstoimproveperformance,SV3.0DataTypes,logicishassingledriver(proceduralassignmentsoracontinuousassignment),canreplaceregandsingledriverwire.(Equivalentto“std_ulogic”inVHDL),Bitsubsallowed,2/24/05,SVLanguageBasics,Enum-enumeratedtypeExplicitlytypedProvidesforcompiletimeerrorchecking,SV3.0DataTypes,/declaredatatypetypedefenuminit,decode,idlefsmstate;fsmstatepstate,nstate;/declarevariablescase(pstate)idle:nstate=init;/dataassignmentinit:nstate=decode;default:nstate=idle;endcase,2/24/05,SVLanguageBasics,OthersEvents,semaphores,mailboxes,stringsandmore!Otherconstructs,suchas:timerealvoidUserdefineddatatypesUserdefineddatatypessuchastypedefandclass,SV3.1aDataTypes,typedefbit1:5bsix;/Definenewtypebsixmy_var;,2/24/05,SVLanguageBasics,PackedandUnpackedArrays,bit7:0b;,bitc7:0;,0,1,2,3,4,5,6,7,0,unused,bit31:0d3:0;,31:0,31:0,31:0,31:0,unused,1,unused,2,unused,3,unused,4,unused,5,unused,6,unused,7,unused,2/24/05,SVLanguageBasics,FixedSizeArraysAlldatatypescanbedeclaredasarraysMultipledimensionssupported,Arrays,bit7:0c1;/packedarrayofbitslogicu7:0;/unpackedarrayintarray832;/sameas:intarray0:70:31;bit3:07:0joe1:10;/10entriesof4bytes,/packedinto32bitsbit1:61:5foo41:81:7;/1:5variesmostrapidly,/followedby1:6,1:7and1:8typedefbit1:5bsix;/Definenewtypebsix1:10foo5;/1to5variesmostrapidlytypedefbsixmemsix0:3;/arrayof4bsixelementsmemsixbar0:7;/arrayof8mem_typeelements,2/24/05,SVLanguageBasics,DynamicArrays-FASTSimilartoafixedsizearray,butsizegivenatruntimeSingledimensiononly,neverpacked,Arrays,inta=new5,/Startwith5elementsb,j;for(j=0;ja.size();j+)/Initializeaj=j;b=a;/Copyadynamicarrayb0=5;$display(a0,b0);/Seebothvaluesa=new100;/Allocate100newintegers/Oldvalueslosta.delete();/Deleteallelements,2/24/05,SVLanguageBasics,QueuesFLEXIBLEVariablesizearraywithautomaticsizingManysearching,sorting,andinsertionmethods(seeLRM)Constanttimeforread,write,andinsertatfrontintj=2,b$=4,5;q.insert(2,j);/0,1,2,3,6Insertbefores2q.insert(4,b);/0,1,2,3,4,5,6Insertwholequeueq.delete(1);/0,2,3,4,5,6Deleteelement#1q.push_front(7);/7,0,2,3,4,5,6Insertatfrontj=q.pop_back();/7,0,2,3,4,5j=6q.push_back(8);/7,0,2,3,4,5,8Insertatbackj=q.pop_front();/0,2,3,4,5,8j=7for(j=0;jvcs+svtbtest.varb.vtop.v-debugsimv,Alwaysusedebugswitchtocatchnullobjectaccess,2/24/05,Agenda,IntroductionGettingStartedLanguageBasicsConnectingtoyourDUTDriving,Sampling,SynchronizingOOPBasicsRandomizationSpawningProcessesFunctionalCoverageTestbenchMethodology,2/24/05,Driving,Sampling,Synchronizing,SignalAccessfromClockingBlockSynchronizationSampleDrive,WhatAreWeGoingtoDiscuss?,2/24/05,UsingtheClockingBlock,ClockingBlocksignalsarereferencedbypre-pendingtheclockingnametothesignal:value=CBarb.grant;/sampleCBarb.request=1;/drive,SignalAccess,AlldrivesmustuseClockingDriveAssignment,clockingCBarb(posedgeclk);defaultinput#1output#0;/#1stepoutputreset=reset_p;outputrequest=request_p;inputgrant=grant_p;endclocking,2/24/05,GettingStartedTestbenchTiming,Thetestbench(program)runsseparatelyfromdesign(module)ClockingblocktriggeredbyclockSamplesjustbeforeclockedge,drivesjustafterclock,SystemVerilogTestbenchinSimulation,clock,Sampleinputs,Driveoutputs,Design,Testbench,2/24/05,GettingStarted-SV3.1aReactiveRegion,Eachtimestepisdividedinto5majorregions(plusPLI)PreponeSamplesignalsbeforeanychanges(#1step)ActiveDesignsimulation(module),includingNBAObservedAssertionsevaluatedaftersignalchangesReactiveTestbenchactivity(program)PostponeReadonlyphase,SystemVerilogSchedulingDetails,clock,prepone,observed,reactive,postpone,data,active,design,sample,assertions,testbench,$monitor,REGION,ACTIVITY,100,100,101,99,Time,2/24/05,Driving,Sampling,Synchronizing,SynchronizetoactiveclockedgespecifiedinclockingblockCBarb;/continueonposedgeofarbiterclkSynchronizetoanyedgeofclockingblocksignalCBarb.grant;/continueonanychangeofsignal(posedgeCBarb.grant);/continueonposedge(negedgeCBarb.grant);/continueonnegedgewait(CBarb.grant);/waitforexpressiontrueSynchronizeonmultiplesignalswith“or”(posedgeCBarb.grantornegedgeCBbus.error);,SignalSynchronization,2/24/05,Driving,Sampling,Synchronizing,Drivesignalsfromclockingblocks:CBbus.request=1;/ClockingdriveCBmandcallATM_HEC.display();,2/24/05,Inheritance,WhydoIwantallthiscomplexity?CodecantreatallcellsinthesamewayCellclassknowshowtoperformactionsCell.display()PrintATMcelldataifImatATMcellPrintEthernetMCAdataifImanethernetpacketPrintSonetframedataifImasonetframePrintUSBpacketdataifImaUSBpacketCodecallingdisplaydoesntneedtoknowwhattypeofcell/packetcellhandlereferencesClassesareself-contained,theyknowhowtoperformactionsonthemselvesbasedontheirtypeSelf-contained,robust,reusablecode.,2/24/05,classPCI64extendsPCI32;reg63:0ad;reg7:0c_be;regpar64,req64,ack64;functionnew();endfunctionendclass/classPCI64,classPCI32;reg31:0ad;reg3:0c_be;regpar,frame,trdy,irdy;functionnew();endfunctionendclass/classPCI32c,InheritanceToReuseExistingCode,Declarebaseclassfirst,Extendclasswithnewfunctionality,2/24/05,classTest5_stimextendsStim;constraintbottleneckdestinside1000:1020;endclass,classTest6_stimextendsStim;constraintthroughputdestinside0:1000,1500;endclass,Inheritance:StartGeneric,DetailsLater,Declarebaseclassfirst,Extendclasswithtestspecificcode,classStim;randreg31:0dest;endclass,2/24/05,Inheritance:Whataboutoverlap?,Whatifbaseandderivedclasseshavepropertiesormethodswiththesamename?Anobjecthandlefromaderivedclassaccessesthechangedpropertyormethod,overridingwhatwastherebefore,classPacket;intda,sa,datype;taskprintit();endtaskendclass,classEthernetextendsPacket;reg47:0da,sa;taskprintit(intdepth);endtaskendclass,2/24/05,Lab2,Optional:VerifytheMemoryController,ObjectiveReadChapter4oftheTutorialVerifyControllersResetVerifyReadandWriteOperationsVerifytheaddressmapTimeAllotted1hour,2/24/05,Agenda,IntroductionGettingStartedLanguageBasicsConnectingtoyourDUTDriving,Sampling,SynchronizingOOPBasicsRandomizationSpawningProcessesFunctionalCoverageTestbenchMethodology,2/24/05,Randomization,WhatAreWeGoingtoDiscuss?,WhyuserandomizationRandomizationoptionsRandomizationofobjectsClassconstraintsanddistributionsIn-Lineconstraintsanddistributions,2/24/05,Randomization,WhyUseRandomization?,AutomaticstimulusgenerationChangethecharacteristicsofthedatadrivingtheDUTRandomselectionoftestsRunknownvalidtestinrandomorderRandomsettingofparametersSelectports,addresses,operationalparametersrandomly.Directedtestingdetectsthebugsyouexpect.Randomtestingdetectsthebugsyoudidnotexpect.,2/24/05,Randomization,RandomizationofObjects,Randomvariablesrandreturnsvalueovertheentirerangerandcrandomcyclicvalueupto8bitsObjectvariablesarerandomizedbycallingtheobjectmethodrandomize().Returnsa1uponsuccess.Themethodisautomaticallyavailabletoclasseswithrandomvariables.Youcancreatepre_randomize()andpost_randomize()methodswhichwillbeautomaticallycalledpre_randomize()setuprandomweightspost_randomize()cleanupcalculationslikeCRC,2/24/05,Randomization,RandomizationofObjects,classPacket;randreg16:0length;randcreg7:0types;/cyclethroughalltypesrandreg7:0payload5;endclass,programtest;Packetp1=new();initialbeginif(!p1.randomize()$display(“Unabletorandomizep1n”);endendprogram,rand:rollingdicerandc:dealingcards,2/24/05,Randomization,ConstrainingRandomness,PurelyrandomstimulustakestoolongtodosomethinginterestingConstraintBlocksallowtheinterestingsubsetofallpossiblestimulusYoucandefineseparate,non-overlappingconstraintsfordifferenttestsEachpossiblesolutiontoyourconstraints,bydefault,willhaveequallikelihood,butyoucancreate“distributions”tomodifythis.Constraintsanddistributionweightscanformthebasisfora“testwriterinterface”toyourtestbench,User-CreatedTest:-subsetoflegalstimulusvectors-subsetoflegalstimulussequences,YourTestbench:-alllegalstimulusvectors-alllegalstimulussequences,SIM,2/24/05,Randomization,ClassConstraintsandDistributions,constraintc_0length0;typeinside2:10,100:107;addrdist0:=40,1:2:=60;datadist0:/40,1:3:/60;,Weightedprobabilities:=assignsweighttoeachelement:/dividesweightevenlyinrange,TheConstraintBlockDistributionscanbevariables,donthavetobeapercentageMultipleconstraintscanbedynamicallyenabled/disabledwithhandle.constraint_mode()Errormessagesaregeneratedforunsolvableconstraints,Distributionsdonothavetoaddupto100%,ValueDist040/100120/100220/100320/100,ValueDist040/160160/160260/160,2/24/05,Randomization,In-LineConstraintsandDistributions,classTransaction;randbit31:0addr,data;constraintc1addrinside0:100,1000:2000;endclassTransactiont=new();s=t.randomize()withaddr50;addr10;/addrisforcedtobeaspecificvaluedriveBus(t);,Constraintsmaybedefinedatthetimeofrandomizationresult=instance.randomize()withconstraints;Allowstest-specificconstraintsIn-lineconstraintsareadditivewithexistingclassconstraintsSupportsallSV3.1aconstraintanddistributiondefinitions,2/24/05,Randomization,Thesolvercanhandlealgebraicfactoring,complexBooleanexpressions,mixedintegerandbitexpressionsandmoreAllconstraintsinteractbi-directionallyKeepinmindrulesregardingprecedence,signextension,truncationandwrap-aroundwhencreatingconstraints,SNPShastheBestInClassconstraintsolver!,classParams;randbit20:0a,b,c,d,e,f;constraintc_0(a+b)0)endclass,2/24/05,Randomization,Variableordering:solvexbeforey;OtherwiseTBsolvesallconstraintssimultaneouslyImplicationOperator:-Ex:(mode=SMALL)-(length10);Conditionaloperator:ifelseifelseBehaveslikeanormal“if”,excepttheconditionalsareevaluatedbi-directionallyGlobalConstraints:xother_object.y;Referencestorandobjectdatamembersintheconstraintsgetsolvedsimultaneously,ConstraintconstructsinSystemVerilog,2/24/05,Randomization,MakeinstancesrandOrtheywontberandomizedWatchoutforsignedvariablesWhatarelegalvaluesforfirstandsecond?Dontrandomizeinnew()constructorAlwayscheckresultofrandomize()Oruse:void