基于flash型单片机二进制模数转换器的温度计解码器外文文献翻译、中英文翻译

Thermometer-to-Binary Decoders for Flash Analog-to-Digital ConvertersAbstract:Decoders for low power, high-speed flash ADCs are investigated. The sensitivity to bubble errors of the ROM decoder with error correction, ones-counter, 4-level folded Wallace-tree, and multiplexer-based decoder are simulated. The ones-counter and multiplexer-based decoder,corresponding to the error insensitive and hardware efficient cases, are implemented in a 130 nm CMOS SOI technology. Measurements yield an ENOB of about 4.1 bit for both, and energy consumption of 80 pJ and 60 pJ, for the respective decoders. Hence we conclude that the MUX-based decoder seems to be a good choice with respect to area, efficiency, and speed.Key words: Thermometer-to-Binary flash ADCs ConvertersI. INTRODUCTIONApplications like ultra-wideband radio and the read channel in hard disk drives generally require high-speed analog-to-digital conversion with resolution four to six bits. These requirements are commonly satisfied by the flash analog-to-digital converter (ADC) architecture 1 that converts the analog input to a binary output with a single stage of parallel comparators, where N is the number of bits in the output, followed by a digital decoder. The comparators compare the input with the quantization levels from a set of reference voltages generated by a resistive ladder and produce a logical output depending on the outcome of the comparison. The output pattern from this stage corresponds to thermometer code and is subsequently translated to binary code by the digital decoder, i.e. the thermometer-to-binary decoder. For a low speed converter the input to the decoder is indeed a perfect thermometer code, but for high speed there may be some erroneous bits in the thermometer code, so called bubbles 2. The bubbles are due to a number of sources 3, e.g., metastability, offset, crosstalk, and bandwidth limitations of the comparators, uncertainty in the effective sampling instant, etc. Hence the decoder must be able to perform well even in the presence of the bubble errors in a high-speed converter. Including requirements on power consumption and throughput, we see that the decoder must be paid significant consideration and trade-off in the design of a high-speed converter. In this work we focus on the design of decoders for low-power, high-speed six-bit ADCs. The work is a part of a larger project where the overall aim is to develop design techniques for implementation of high-performance analog circuits in CMOS silicon-on-insulator technology. We have investigated four types of thermometer-to-binarydecoders presented in Sec. II, through behavioral level simulations of the sensitivity to bubble errors presented in Sec. III, from which we have chosen two decoders that have been implemented in a 130 nm CMOS SOI technology. The measurement results are presented in Sec. IV and the conclusions are given in Sec. V.II. DECODERSFour different types of thermometer-to-binary decoders are presented. Two of them, the ROM and folded Wallace tree decoder,are only studied on behavioral level. The ones-counter decoder and the MUX-based decoder have also been implemented in two flash ADCs in a CMOS silicon-on-insulator technology. The corresponding results are thereby based on transistor level simulation results and measurements.A. ROMA common and straightforward approach to encode the thermometer code is to use a gray or binary-encoded ROM. The appropriate row m in the gray encoded ROM is selected by using a row decoder that has the output of comparator m and the inverse of comparator m + 1 as inputs. The output m of the row decoder, connected to memory row m, is high if the output of comparator m is high and the output of comparator m + 1 is low. The row decoder can be realized by, e.g., a number of 2-input NAND gates, where one input to each NAND gate is inverted. This type of row decoder selects multiple rows if a bubble error occurs, which introduces large errors in the output of the decoder 3, 4. Considering single bubble errors only, these errors can be corrected by using 3-input NAND gates, as shown in Fig. 1. The 3-input NAND gates remove all bubble errors if they are separated by at least three bits in the thermometer scale. The main advantage of the ROM decoder approach is its regular structure that is straightforward to design. A disadvantage is that more bubble errors are introduced as the conversion speed increases and a more advanced bubble error correction scheme is required. As the complexity of the bubble error correction circuit increases, its propagation delay does in general also increase. The longer propagation delay reduces the maximum sampling rate of the overall decoder if not pipelining is applied. The increased complexity of the circuit consumes more chip area and will likely consume more power 5, 6.Figure 1Another bubble error suppression technique is the butterfly sorting technique presented in 7. Applying this technique the bubbles are propagated upwards in the thermometer scale until the thermometer code is free from bubbles. Then the ROM decoder is used to encode the bubble-free thermometer code to binary code. In 7 the butterfly sorter only has eight levels. Bubbles further away from the transition level than eight positions cannot be removed. To guarantee that no bubbles will be present in the thermometer output code the depth of the butterfly sorter must be equal to the number of comparators, i.e.,.B. Ones-CounterThe output of a thermometer-to-binary decoder is the number of ones on the input represented in, e.g., gray or binary code. Hence a circuit counting the number of ones in the thermometer code, i.e., a ones-counter, can be used as the decoder 8. The use of a ones-counter gives global bubble error suppression 3, 6, 8. Another benefit of the approach is that a suitable ones-counter topology may be selected by trading speed for power. From this tradeoff the Wallace tree topology 9, illustrated in Fig. 2, is a good candidate as a decoder for high-speed converters 3, 6, 10.Figure 2In this work we use a tree of full adders (FAs) that reduce the 63 inputs to 10 outputs, as illustrated by Fig. 3. The different signal paths through the decoder are matched, i.e., each signal passes through the same number of full adders, where each input has approximately the same propagation delay to the output. The propagation delay of the signals through the decoder should thereby be approximately the same for all signals. The decoding of the 10 outputs to the binary value is done using MATLAB. The depth of the tree is thereby limited to six levels in the hardware implementation presented in the next section, which enables the ADC to operate at higher speed. In an improved design the complete decoding to a binary output can be accomplished onchip by introducing pipelining in the decoder. Further optimization of the sizing of each FA can also improve the performance to some degree.C. Folded Wallace TreeFigure 3In a folded flash ADC, the idea is to reduce the amount of hardware by using the same comparator for different reference voltages 11. This is the idea of the folded Wallace tree decoder shown in Fig. 4 6. The size of the Wallace tree and the delay depend on the number of bits that are added, i.e. the width of the base of the tree. The idea is to split the output of the comparators into different intervals. They are multiplexed to a reduced Wallace tree decoder, which is smaller compared with the full one 3. A full adder may be realized from three 2:1 multiplexers with two multiplexers in the critical path.D. MUX-BasedThe multiplexer-based decoder consists entirely of multiplexers, as illustrated in Fig. 5, where N = 4 bit. It requires less hardware and has a shorter critical path than a ones-counter decoder 3, 5. In addition it gives bubble error suppression, although the suppression is slightly lower than for a ones-counter decoder 5. Another advantage of the multiplexer-based decoder is the more regular structure than, e.g., the ones-counter decoder. This is a major benefit in the layout of the circuit. The multiplexers used in this work are based on transmission gates. An inverter is used as a buffer in each transmission gate multiplexer.Figure 4III. B EHAVIORAL LEVEL SIMULATIONThe effect of the chosen decoder topology on the ADC performance was evaluated by behavioral level simulations for the four different architectures. The timing difference t between the clock signal and the input signal to each comparator was modeled by a Gaussian distribution, according to 。The timing difference is of concern if no sample-and-hold circuit is used, which is acceptable for converters with a resolution less than 6 bits 12. The timing difference mismatch between the comparators introduces bubble errors. The bubble errors have significant effect on the ADC performance, e.g., in terms of effective number of bits (ENOB). The performance of the decoders can thereby be compared by plotting the ENOB as a function of the standard deviation .A MATLAB model was developed to enable the performance comparison. In the behavioral level simulations a single tone sinusoid input were assumed according to.Figure 5where VFS is the full-scale voltage. An approximation of the maximum time derivative of the input is The effect of the timing difference is therefore an uncertainty in the sampled input voltage, . Using (3), the maximum uncertainty in the sampled input voltage has a Gaussian distribution according to .The uncertainty is added to the input in the simulations. The sampling time uncertainty is therefore modeled as an offset voltage on the input of the comparators, given by (4). This model was used in the MATLAB simulations of a flash ADC with the four different decoders, i.e., the ROM decoder with 3-input NAND gates for bubble error correction, the ones-counter decoder, the MUX-based decoder, and the 4-level folded Wallace tree decoder. The results of the simulations are shown in Fig. 6. In Fig. 6 the average ENOB of a 6-bit ADC is plotted as a function of the standard deviation of the timing difference between he clock lines and the signal lines, i.e., . As seen in the figure the performance of the MUX-based decoder is about the same as for the ROM decoder with 3-input NAND gates used for the bubble error correction. Note that the MUX-based decoder has no special bubble error correction circuits. It is also seen that the ones-counter decoder has better performance than both the ROM decoder and the MUXbased decoder. Finally, the 4-level folded Wallace tree decoder has a slightly lower average ENOB than the ones-counter. The reason for this is that the folded Wallace tree topology is more sensitive to bubble errors at the thermometer input levels that are connected to the 3-input OR gates shown in Fig. 4, since these levels control the MUX seen in the same figure.Figure 6IV. MEASUREMENT RESULTSFrom the behavioral simulation we saw that the ones-counter decoder was the most insensitive to bubble errors. Of the other decoders, the MUX-based stands out as having the lowest hardware cost, but a somewhat higher sensitivity to bubble errors. We choose these two decoders for hardware implementation in 6-bit, 1-GHz ADCs in a 130 nm CMOS silicon-on-insulator technology. To save power, a sample-and-hold circuit is avoided in the design 12, and the decoders are implemented without pipelining. To avoid excessive delay in the ones-counter decoder the adder tree is only partially implemented. Hence six more full adders are required, whose operation instead are performed through post processing in MATLAB and their contribution to the power consumption is extrapolated. The total chip areas are 4.1 and 2.9 , and the core areas are 0.7 and 0.4 for the ones-counter and MUX-based ADCs, respectively.The dynamic performance is evaluated by applying a single tone sinusoidal input to the ADC and obtaining its spectral measures from a plot of the output spectrum. An estimate of the maximum sampling frequency, , is first derived. With a low frequency (495 kHz) sinusoidal input the sampling frequency is swept from 7 MHz up to sampling frequencies above 1 GHz. However, the used measurement equipment only allowed sampling of the output at a few discrete time instances relative to the clock, which limited the measurements to only be accurate within time periods where the sampling and the stable output could be made coincidental. 基于flash型单片机二进制模数转换器的温度计解码器摘要：研究低耗、高速的flash ADCs型解码器 。我们用ones-counter，深度为4的折叠式的Wallace-tree、以及基于MUX的译码器来仿真ROM译码器对于纠正泡沫错误的灵敏度。ones-counter和基于MUX的译码解码器，可以在130纳米CMOS SOI技术下实现，适用于对误差要求不高和硬件高效的情况。Ones-counter 和基于MUX型的解码器测得ENOB的量产率都为4.1比特，能源消耗分别为80PJ和60PJ。因此，我们得出结论，基于MUX型的解码器是在面积，效率，速度方面来说都不错的选择。关键词：温度计码到二进制 flash ADCs 转换器I.简介通常只有四到六个比特的高速模数转换才能应用硬盘驱动器里超宽带无线电和硬盘读通道。flash模拟信号到数字信号转换器（ADC）的系统架构通常可以将模拟信号输入转换为2进制输出（转换式为），其中N是输出的位数，由数字解码器跟踪得到的。比较器通过把输入与梯形电阻网络产生的量化参考电压进行比较后在输出端输出逻辑电平。 从这一阶段的输出的测试图与温度计代码相对应，并随后由数字解码器转化为二进制代码，也就是温度计到二进制解码器。对于低速转换器来说，这种输入到解码器确实是完善的温度计代码，但若用于高速在温度计代码中可能有一些二进制位错误，即所谓的气泡。该气泡的产生是有很多原因的，如亚稳态，偏移比较器的串扰，和带宽的限制，有效采样时刻的不确定性等。因此，解码器必须是能在高速转换器存在气泡错误的情况下正常工作。我们发现在设计高速转换器的时候必须再三考虑并且权衡解码器的功耗和吞吐量的要求。这项研究中，我们专注于设计低功耗的解码器和6位高速ADCs。最终的目标是开发设计能在CMOS硅绝缘体上实现的高性能的模拟电路技术，这项工作是这个目标中的一部分。在第二部分我们已经研究了四种类型的温度计到二进制解码器的性能，在第三阶段通过行为级仿真阐述了解码器对气泡误差的精确度。我们从中选择了两个已被实施130nm CMOS SOI技术的解码器。测量结果将在第四届部分展现。第五部分将会给出最终结论。 II.解码器描述了四种不同类型的温度计码到二进制解码译码器。其中有两种是ROM式、折叠Wallace tree式计码译码器，都只研究了行为级。ones-counter解码器和在基于MUX的解码器已经在两个硅基CMOS技术的flashADCs上实现了。基于晶体管级仿真的结果和测量从而得到了结果。A. ROM温度计码编码的一个常见和简单的方法是使用格雷码或二进制编码的ROM。利用有m个输出比较器和m+1个反相比较器输入的行编码器对格雷码编码器ROM的相应的m行进行编码。m行译码器的输出，连接到存储器的m行，如果比较器m的输出为高就是高，那比较器m+ 1的输出就是低的。行译码器可以被实现的，例如，大量的2输入与非门，每个与非门两个输入中有一个是反相的。如果存在气泡错误会引起解码器在输出有很大的误差，这种类型的行译码器选择多行。当只考虑到单个气泡错误时，这些错误可以通过使用3输入与非门来校正，如图.1。 3输入与非门可以除去间隔至少有三位的温度计刻度以上的所有气泡错误。图1该ROM解码方法优点是结构设计简单。缺点是引起更多的泡沫误差、转换速度提高就需要更有效的气泡纠错方案。当气泡的纠错电路的复杂性增加，它的传播延迟时间一般也会增加。如果没有采用流水线型解码器那传播延迟时间会变长会降低整体的最大采样率。增加电路的复杂性会浪费更多的芯片资源、消耗更多的能量。另一个泡沫误差抑制技术是蝶型排序技术中提出了7。应用这种技术的气泡会在温度计的刻度向上传播，直到温度计码里完全没有气泡。然后ROM解码器将无气泡的温度计代码编码成二进制码。在7蝶分拣机只能有八个级别。气泡如果距离它的转换高度太远就无法被去除。为了保证没有气泡将存在于输出的温度计码中深度蝶形排序拣机数目必须等于比较器的数目，即。 B.ones-counter二进制温度计码解码器的输出是对那些输入数的表述，例如，格雷码或二进制代码。因此，用一个电路统计温度计码的数量，也就是说，ones-counter可以用作译码器8。使用ones-counter抑制了全局的泡沫误差3，6，8。该方法的另一个好处是，合适的ones-counter拓扑结构可以通过压低速度来换取低功耗。从这种折衷的Wallace tree型拓扑9，如图2所示，是可以作为高速转换器解码器的一个很好的候补3，6，10。图2在这项工作中，我们使用全加器（FAs）型的树将63输入降低为10输出，如图.3.所示，不同的信号路径通过相匹配的译码器，即每个信号经过相同数量的全加器，其中每个输入到输出具有大致相同的传播延迟时间。信号通过解码器的传播延迟时间也因此大概都是一样的。通过MATLAB这个软件可以完成将10个输出转换到二进制值的译码。如何实现将树的深度限制为六将在下一节介绍，这样可以使ADC更高速的运转。在一个通过采用流水线型解码器改进过的设计可以实现到二进制解码完整的输出。进一步优化每个FA的大小也可以在一定程度上提高性能。 C.折叠式Wallace tree 型在一个折叠的flash ADC中，这个方式是在不同的参考电压下使用相同的比较器为了节省硬件资源。这是图4中所示的折叠Wallace tree的译码器的思路6。Wallace tree和延迟时间的大小取决于数被添加的比特数，即Wallace tree树的基级的宽度。这个想法是将比较器的输出拆分为不同的区间。他们被多路复用用来简化Wallace tr