4032 CMOS 3位正逻辑串行加法器

MOTOROLA CMOS LOGIC DATAMC14032B MC14038B 128 ? ? ? The MC14032B and MC14038B triple serial adders have the clock and carry reset inputs common to all three adders. The carry is added on the positivegoing clock transition for the MC14032B, and on the negative going clock transition for the MC14038B. Typical applications include serial arithmetic units, digital correlators, digital servo control systems, datalink computers, and flight control computers. Buffered Outputs SinglePhase Clocking Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range. PinforPin Replacement for CD4032B and CD4038B. MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 V lin, lout Input or Output Current (DC or Transient), per Pin 10 mA PD Power Dissipation, per Package 500 mW Tstg Storage Temperature 65 to + 150 ?C TL Lead Temperature (8Second Soldering) 260 ?C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic “P and D/DW” Packages: 7.0 mW/?C From 65?C To 125?C Ceramic “L” Packages: 12 mW/?C From 100?C To 125?C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. LOGIC DIAGRAMS (ONE SECTION AND COMMON INPUTS SHOWN) B A INVERT CARRY RESET CLOCK TO NEXT STAGE TO NEXT STAGE B A INVERT CARRY RESET CLOCK D R Q C DQ C SS D R Q C DQ C MC14032BMC14038B ? SEMICONDUCTOR TECHNICAL DATA Motorola, Inc. 1995 REV 3 1/94 ? ? L SUFFIX CERAMIC CASE 620 ORDERING INFORMATION MC14XXXBCPPlastic MC14XXXBCLCeramic MC14XXXBDSOIC TA = 55 to 125C for all packages. P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B BLOCK DIAGRAM CARRY RESET6 CLOCK3 INVERT 32 B3 14 A3 15 ADDER 31 S3 VDD = PIN 16 VSS = PIN 8 INVERT 25 B2 12 A2 13 ADDER 24 S2 INVERT 17 B1 11 A1 10 ADDER 19 S1 MOTOROLA CMOS LOGIC DATA 129 MC14032B MC14038B ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VDD Vdc 55?C 25?C 125?C Unit Characteristic Symbol VDD Vdc Min Max Min Typ # Max Min Max Unit Output Voltage“0” Level Vin = VDD or 0 “1” Level Vin = 0 or VDD VOL 5.0 10 15 0.05 0.05 0.05 0 0 0 0.05 0.05 0.05 0.05 0.05 0.05 Vdc “1” Level Vin = 0 or VDD VOH 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Input Voltage“0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) VIL 5.0 10 15 1.5 3.0 4.0 2.25 4.50 6.75 1.5 3.0 4.0 1.5 3.0 4.0 Vdc “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) VIH 5.0 10 15 3.5 7.0 11 3.5 7.0 11 2.75 5.50 8.25 3.5 7.0 11 Vdc Output Drive Current (VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) IOH 5.0 5.0 10 15 3.0 0.64 1.6 4.2 2.4 0.51 1.3 3.4 4.2 0.88 2.25 8.8 1.7 0.36 0.9 2.4 mAdc (VOL = 0.4 Vdc)Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) IOL 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.88 2.25 8.8 0.36 0.9 2.4 mAdc Input Current Iin 15 0.1 0.00001 0.1 1.0 Adc Input Capacitance (Vin = 0) Cin 5.0 7.5 pF Quiescent Current (Per Package) IDD 5.0 10 15 5.0 10 20 0.005 0.010 0.015 5.0 10 20 150 300 600 Adc Total Supply Current* (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 IT = (0.96 A/kHz) f + IDD IT = (1.93 A/kHz) f + IDD IT = (2.80 A/kHz) f + IDD Adc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the ICs potential performance. *The formulas given are for the typical characteristics only at 25?C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.003. PIN ASSIGNMENT 13 14 15 16 9 10 11 125 4 3 2 1 8 7 6 B2 A2 B3 A3 VDD S1 A1 B1 S2 C INV 3 S3 VSS INV 1 CARRY RESET INV 2 MOTOROLA CMOS LOGIC DATAMC14032B MC14038B 130 SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25?C) Characteristic Symbol VDD Vdc Min Typ # Max Unit Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL 5.0 10 15 100 50 40 200 100 80 ns Propagation Delay Time A, B or Invert to Sum tPLH, tPHL = (1.7 ns/pF) CL + 195 ns tPLH, tPHL = (0.66 ns/pF) CL + 87 ns tPLH, tPHL = (0.5 ns/pF) CL + 65 ns tPLH, tPHL 5.0 10 15 280 120 90 1400 300 230 ns Clock to Sum tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/pF) CL + 147 ns tPLH, tPHL = (0.5 ns/pF) CL + 110 ns 5.0 10 15 500 180 135 2400 600 450 ns Input Setup Time tsu 5.0 10 15 10 10 10 10 0 0 ns Clock Pulse Frequency fcl 5.0 10 15 4.0 10 12 1.0 2.5 4.0 MHz Clock Rise and Fall Times tTHL, tTLH 5.0 10 15 1 5 5 4 s * The formulas given are for the typical characteristics only at 25?C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the ICs potential performance. TIMING DIAGRAMS MC14032BMC14038B A B C INV CR S WORD 1 + WORD 2WORD 3 + WORD 4 TRUE SUMCOMPLEMENTED SUM WORD 1: WORD 2: 0.0111100 0.0110010 = = +60 +50 0.1101110 = +110 WORD 3: WORD 4: 1.1011011 1.1001110 = = 37 50 1.0101001 = 87 WORD 1: WORD 2: 1.1000011 1.1001101 = = 61 51 1.0010000 = 112 WORD 3: WORD 4: 0.0100100 0.0110001 = = +36 +49 0.1010101 = +85 TRUE SUMCOMPLEMENTED SUM WORD 1 + WORD 2WORD 3 + WORD 4 A B C INV CR S NOTE: Unused input pins must be connected to either VDD or VSS. MOTOROLA CMOS LOGIC DATA 131 MC14032B MC14038B Figure 1. Typical Output Source Test CircuitFigure 2. Typical Output Sink Test Circuit VDS = VOH VDD VOHVDD = VGS VDD VSS IOH A1 B1 INV1 A2 B2 INV2 A3 B3 INV3 CLOCK CRS3 S2 S1 EXTERNAL POWER SUPPLY EXTERNAL POWER SUPPLY VDS = VOL VOLVDD = VGS VDD VSS IOL A1 B1 INV1 A2 B2 INV2 A3 B3 INV3 CLOCK CRS3 S2 S1 Figure 3. Power Dissipation Test Circuit and Waveforms VDD VDD VSS 500 pF 0.01 F CERAMIC PROGRAMMABLE PULSE GENERATOR A1 B1 INV1 A2 B2 INV2 A3 B3 INV3 CLOCK CRS3 S2 S1 CL CL CL CLOCK A,B 20 ns20 ns VDD VSS VDD VSS tTLHtTHL 90% 10% 50% 90% 10% VARIABLE WIDTH ID MOTOROLA CMOS LOGIC DATAMC14032B MC14038B 132 Figure 4. Switching Time Test Circuit and Waveforms VDD VSS PROGRAMMABLE PULSE GENERATOR A1 B1 INV1 A2 B2 INV2 A3 B3 INV3 CLOCK CRS3 S2 S1 CL CL CL MC14038B MC14032B A B CLOCK SUM 50% 50% 50% tPLHtPHLtPLHtPHL tTLHtTHL VDD VSS VDD VSS VDD VSS VOH VOL tsu A B CLOCK SUM 50% 50% 50% tPHLtPLHtPHLtPLH tTLHtTHL tsu VDD VSS VDD VSS VDD VSS VOH VOL 90% 50% 10% 90% 50% 10% MOTOROLA CMOS LOGIC DATA 133 MC14032B MC14038B OUTLINE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE 64808 ISSUE R NOTES: 1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.CONTROLLING DIMENSION: INCH. 3.DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4.DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5.ROUNDED CORNERS OPTIONAL. A B F C S H G D J L M 16 PL SEATING 18 916 K PLANE T M A M 0.25 (0.010)T DIMMINMAXMINMAX MILLIMETERSINCHES A0.7400.77018.8019.55 B0.2500.2706.356.85 C0.1450.1753.694.44 D0.0150.0210.390.53 F0.0400.701.021.77 G0.100 BSC2.54 BSC H0.050 BSC1.27 BSC J0.0080.0150.210.38 K0.1100.1302.803.30 L0.2950.3057.507.74 M0 10 0 10 S0.0200.0400.511.01 ? L SUFFIX CERAMIC DIP PACKAGE CASE 62010 ISSUE V NOTES: 1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.CONTROLLING DIMENSION: INCH. 3.DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4.DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. A B T F E G NK C SEATING PLANE 16 PLD S A M 0.25 (0.010)T 16 PLJ S B M 0.25 (0.010)T M L DIMMINMAXMINMAX MILLIMETERSINCHES A0.7500.78519.0519.93 B0.2400.2956.107.49 C0.2005.08 D0.0150.0200.390.50 E0.050 BSC1.27 BSC F0.0550.0651.401.65 G0.100 BSC2.54 BSC H0.0080.0150.210.38 K0.1250.1703.184.31 L0.300 BSC7.62 BSC M0 15 0 15 N0.0200.0400.511.01 ? 169 18 MOTOROLA CMOS LOGIC DATAMC14032B MC14038B 134 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B05 ISSUE J NOTES: 1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.CONTROLLING DIMENSION: MILLIMETER. 3.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4.MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 18 169 SEATING PLANE F J M RX 45? G 8 PLPB A M 0.25 (0.010)BS T D K C 16 PL S B M 0.25 (0.010)AST DIMMINMAXMINMAX INCHESMILLIMETERS A9.8010.000.3860.393 B3.804.000.1500.157 C1.351.750.0540.068 D0.350.490.0140.019 F0.401.250.0160.049 G1.27 BSC0.050 BSC J080.009 K040.009 M0 7 0 7 P5.806.200.2290.244 R0.250.500.0100.019 ? How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;JAPAN: Nippon Motorola Ltd.; TatsumiSPDJLDC, 6F SeibuButsuryuCenter, P.O. Box 20912; Phoenix, Arizona 85036.or 60230354543142 Tatsumi KotoKu, Tokyo 135, Japan. 038135218315 MFAX: RMFAX0 TOUCHTONE 6022446609ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http:/DesignNET.com51 Ting Kok Road, Tai Po, N.T., Hong Kong. 85226629298 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer a