卷积编码和Viterbi译码

卷积编码和Viterbi译码摘要本文的目的是向读者介绍了前向纠错技术的卷积编码和Viterbi译码。前向纠错的目的（FEC）的是改善增加了一些精心设计的冗余信息，正在通过信道传输数据的通道容量。The process of adding this redundant information is known as channel coding.在添加这种冗余信息的过程称为信道编码。Convolutional coding and block coding are the two major forms of channel coding.卷积编码和分组编码是两个主要的渠道形式编码。Introduction 简介 The purpose of forward error correction (FEC) is to improve the capacity of a channel by adding some carefully designed redundant information to the data being transmitted through the channel.前向纠错的目的（FEC）的是改善增加了一些精心设计的冗余信息，正在通过信道传输数据的通道容量。 The process of adding this redundant information is known as channel coding.在添加这种冗余信息的过程称为信道编码。Convolutional coding and block coding are the two major forms of channel coding.卷积编码和分组编码是两个主要的渠道形式编码。 Convolutional codes operate on serial data, one or a few bits at a time.卷积码串行数据操作，一次一个或数位。Block codes operate on relatively large (typically, up to a couple of hundred bytes) message blocks.分组码操作比较大（通常，多达几百个字节的情侣）消息块。 There are a variety of useful convolutional and block codes, and a variety of algorithms for decoding the received coded information sequences to recover the original data.有很多有用的分组码和卷积多种，以及接收解码算法编码信息的DNA序列来恢复原来的各种数据。The reader is advised to study the sources listed in the bibliography for a broader and deeper understanding of the digital communications and channel-coding Convolutional encoding with Viterbi decoding is a FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by additive white gaussian noise (AWGN).卷积编码和Viterbi译码前向纠错技术，是一种特别适合于在其中一个已损坏的发射信号加性高斯白噪声（AWGN）的主要通道。 You can think of AWGN as noise whose voltage distribution over time has characteristics that can be described using a Gaussian, or normal, statistical distribution, ie a bell curve.你能想到的AWGN信道的噪声，其电压分布也随着时间的推移，可以说是用高斯，或正常，统计分布特征，即一钟形曲线。 This voltage distribution has zero mean and a standard deviation that is a function of the signal-to-noise ratio (SNR) of the received signal.这个电压分布具有零均值和标准差这是一个信号与噪声比接收信号的信噪比（SNR）函数。 Lets assume for the moment that the received signal level is fixed.让我们承担起接收到的信号电平是固定的时刻。Then if the SNR is high, the standard deviation of the noise is small, and vice-versa.这时如果信噪比高，噪声标准偏差小，反之亦然。 In digital communications, SNR is usually measured in terms of E b /N 0 , which stands for energy per bit divided by the one-sided noise density.在数字通信，信噪比通常是衡量Eb/N0的它代表噪声密度双面能源每比特除以之一。 Convolutional codes are usually described using two parameters: the code rate and the constraint length.卷积码通常是描述使用两个参数：码率和约束长度。 The code rate, k/n, is expressed as a ratio of the number of bits into the convolutional encoder (k) to the number of channel symbols output by the convolutional encoder (n) in a given encoder cycle.码率k/n，是表示为比特数为卷积编码器（十一）信道符号卷积编码器输出的编码器在给定的周期（N）的数量之比。 The constraint length parameter, K, denotes the length of the convolutional encoder, ie how many k-bit stages are available to feed the combinatorial logic that produces the output symbols.约束长度参数，钾，表示该卷积编码器的“长度”，即有多少K位阶段提供饲料的组合逻辑，产生输出符号。 Closely related to K is the parameter m, which indicates how many encoder cycles an input bit is retained and used for encoding after it first appears at the input to the convolutional encoder. K是密切相关的参数米，这表明有多少位的输入编码器周期被保留，用于编码后第一次在卷积编码器输入的出现。 The m parameter can be thought of as the memory length of the encoder.的m参数可以被认为是编码器的记忆长度。 In this tutorial, and in the example source code, I focus on rate 1/2 convolutional codes.在本教程中，并在此示例的源代码，我集中精力率1 / 2卷积码。 Viterbi decoding was developed by Andrew J. Viterbi, a founder of Qualcomm CorporatioViterbi decoding is one of two types of decoding algorithms used with convolutional encoding-the other type is sequential decoding. Viterbi译码是一种两个卷积编码与解码，其他类型的算法类型的顺序解码。 Sequential decoding has the advantage that it can perform very well with long-constraint-length convolutional codes, but it has a variable decoding time.序贯解码的优点，它可以执行得很好，长期约束卷积码的长度，但它有一个变量解码时间。Viterbi decoding has the advantage that it has a fixed decoding time.维特比解码的优点是它有一个固定的解码时间。 It is well suited to hardware decoder implementation.它非常适合于硬件解码器。 But its computational requirements grow exponentially as a function of the constraint length, so it is usually limited in practice to constraint lengths of K = 9 or less.但它的计算需求的增长作为约束长度功能指数，因此它是在实践中通常是有限的约束长度的K = 9或更少。 Stanford Telecom produces a K = 9 Viterbi decoder that operates at rates up to 96 kbps, and a K = 7 Viterbi decoder that operates at up to 45 Mbps.斯坦福大学电信生产的K = 9的Viterbi解码器，速率高达96 Kbps的运作，和K = 7维特比解码器，以高达45 Mbps的操作。 Advanced Wireless Technologies offers a K = 9 Viterbi decoder that operates at rates up to 2 Mbps.先进的无线技术提供了一个K = 9的Viterbi解码器，速率高达每秒2兆比特运作。 NTT has announced a Viterbi decoder that operates at 60 Mbps, but I dont know its commercial availability.日本NTT公司宣布Viterbi解码器，在60 Mbps的工作，但我不知道它的商业可用性。 Moores Law applies to Viterbi decoders as well as to microprocessors, so consider the rates mentioned above as a snapshot of the state-of-the-art taken in early 1999.摩尔定律适用于维特比解码器，以及微处理器，因此可以考虑提到作为先进设备，在1999年初采取了最先进的快照以上的税率。 For years, convolutional coding with Viterbi decoding has been the predominant FEC technique used in space communications, particularly in geostationary satellite communication networks, such as VSAT (very small aperture terminal) networks.多年来，卷积编码和Viterbi译码一直是主要的FEC技术，特别是在地球静止卫星通信网络，如VSAT（甚小孔径终端）网络，在空间通信中使用。 I believe the most common variant used in VSAT networks is rate 1/2 convolutional coding using a code with a constraint length K = 7.我认为最常见的变异率VSAT网络使用的是1 / 2卷积编码使用约束长度为k = 7的代码。 With this code, you can transmit binary or quaternary phase-shift-keyed (BPSK or QPSK) signals with at least 5 dB less power than youd need without it.有了这个代码，可以传送二进制或四相相移键控（BPSK调制或QPSK），至少有5分贝以下的权力比你没有它需要的信号。 Thats a reduction in Watts of more than a factor of three!这是在瓦，比三因素更能减少！ This is very useful in reducing transmitter and/or antenna cost or permitting increased data rates given the same transmitter power and antenna sizes.这对于减少发射器和/或天线费用率上升的数据或允许给予同样的发射功率和天线尺寸非常有用。 Many radio channels are AWGN channels, but many, particularly terrestrial radio channels also have other impairments, such as multipath, selective fading, interference, and atmospheric (lightning) noise.许多无线电频道AWGN信道，但是很多，尤其是地面广播频道也有其他障碍，如多路径，选择性衰落，干扰和大气（闪电）的噪声。 Transmitters and receivers can add spurious signals and phase noise to the desired signal as well.发射机和接收机的杂散信号，并可以添加到所需的相位噪声信号以及。 Although convolutional coding with Viterbi decoding might be useful in dealing with those other problems, it may not be the best technique.虽然卷积编码和Viterbi译码可能会与那些其他问题时非常有用，它未必是最好的技术。 In the past several years, convolutional coding with Viterbi decoding has begun to be supplemented in the geostationary satellite communication arena with Reed-Solomon coding.在过去的几年里，卷积编码和Viterbi译码已开始在地球静止卫星通信领域的补充与Reed - Solomon编码。 The two coding techniques are usually implemented as serially concatenated block and convolutional coding.这两个编码技术通常为串行级联卷积编码块。 Typically, the information to be transmitted is first encoded with the Reed-Solomon code, then with the convolutional code.通常情况下，要传输的信息进行编码，首先与Reed - Solomon码再与卷积码。 On the receiving end, Viterbi decoding is performed first, followed by Reed-Solomon decoding.在接收端，维特比解码首先执行，由里德所罗门解码遵循。 This is the technique that is used in most if not all of the direct-broadcast satellite (DBS) systems, and in several of the newer VSAT products as well.这是认为，如果不是用于直接广播卫星（DBS）系统中的所有最，并在较新的甚小孔径终端产品，以及一些技术。At least, thats what the vendors are advertising.Recently (1993) a new parallel-concatenated convolutional coding technique known as turbo coding has emerged.最近（1993年）一个新的并行级联卷积编码技术，作为涡轮编码称为出现了。 Initial hardware encoder and decoder implementations of turbo coding have already appeared on the market.初始硬件编码器和解码器的Turbo编码的实现已经出现在市场上。 This technique achieves substantial improvements in performance over concatenated Viterbi and Reed-Solomon coding.这种技术实现了级联的Viterbi和Reed - Solomon编码可观的性能改进。 A variant in which the codes are product codes has also been developed, along with hardware implementations.其中一个变种的代码是产品代码也被开发出来，随着硬件实现。 Check the appropriate sources listed in the bibliography for more information on turbo coding and turbo code devices.说明算法（第一部分） The steps involved in simulating a communication channel using convolutional encoding and Viterbi decoding are as follows:在模拟通信信道卷积编码和Viterbi使用解码所涉及的步骤如下： （1）Generate the data to be transmitted through the channel-result is binary data bits 生成的数据将通过渠道传播的结果，是二进制数据位。 Convolutionally encode the data-result is channel symbol（2）卷积编码的数据符号的结果是通道。 Map the one/zero channel symbols onto an antipodal baseband signal, producing transmitted channel symb（3）地图一/零通道符号上一对极基带信号，传输信道的符号生产。Add noise to the transmitted channel symbols-result is received channel symb（4）添加噪声的传播通道符号，结果收到的频道符号。 （5）Quantize the received channel levels-one bit quantization is called hard-decision, and two to n bit quantization is called soft-decision (n is usually three or f量化接收通道水平，一比特量化称为硬判决，两个量化到N位被称为软判决（N通常三，四）。 （6）Perform Viterbi decoding on the quantized received channel symbols-result is again binary data bits 维特比译码进行量化上收到的频道符号，结果又是二进制数据位。 （7）Compare the decoded data bits to the transmitted data bits and count the number of errors.比较解码数据位传输的数据位和计算错误的数量。 Generating the Data 数据生成 Generating the data to be transmitted through the channel can be accomplished quite simply by using a random number generator.生成要发送的数据通过可以通过使用随机数生成器很简单的通道。 One that produces a uniform distribution of numbers on the interval 0 to a maximum value is provided in C: rand () .用于产生均匀分布的区间数0上，最高值是提供在C：rand ()。 Using this function, we can say that any value less than half of the maximum value is a zero; any value greater than or equal to half of the maximum value is a one.使用这一功能，我们可以说，任何小于最大值的一半是零;任何值大于或等于最大值的一半是另一个。 卷积编码数据 卷积编码的数据是通过使用一个移位寄存器和执行相关的组合逻辑模双增加。 (A shift register is merely a chain of flip-flops wherein the output of the nth flip-flop is tied to the input of the (n+1)th flip-flop. Every time the active edge of the clock occurs, the input to the flip-flop is clocked through to the output, and thus the data are shifted over one stage.) The combinatorial logic is often in the form of cascaded exclusive-or gates. （一移位寄存器仅仅是一个连锁触发器，其中第n个触发器的输出是联系在一起的第（n +1）个触发器输入。每次时钟的有效边沿时，输入在触发器的时钟到输出，因此，数据通过一个阶段的转变。）的组合逻辑往往是在级联异或门的形式。 As a reminder, exclusive-or gates are two-input, one-output gates often represented by the logic symbol shown below,作为提醒，异或门的两个输入，一个输出盖茨代表多为如下所示的逻辑符号， that implement the following truth-table:实现下面的真值表： Input A 输入A Input B 输入B Output 输出 (A xor B) （异或乙） 0 0 0 0 0 0 0 0 1 一 1 一 1 一 0 0 1 一 1 一 1 一 0 0 The exclusive-or gate performs modulo-two addition of its inputs.异或门实现模其输入双增加。 When you cascade q two-input exclusive-or gates, with the output of the first one feeding one of the inputs of the second one, the output of the second one feeding one of the inputs of the third one, etc., the output of the last one in the chain is the modulo-two sum of the q + 1 inputs.当您级联Q两输入异或门，与第一次喂养一对的第二个项目投入，产出的第二个食的第三个，等等，一个一个的输入输出输出在链中的最后一个是模双的Q + 1输入的总和。 Another way to illustrate the modulo-two adder, and the way that is most commonly used in textbooks, is as a circle with a + symbol inside, thus:另一种方式来说明模，两个加法器，而这是最常用的教科书的使用方式，是一个有+符号里面。Now that we have the two basic components of the convolutional encoder (flip-flops comprising the shift register and exclusive-or gates comprising the associated modulo-two adders) defined, lets look at a picture of a convolutional encoder for a rate 1/2, K = 3, m = 2 code:现在，我们有两个卷积编码器（触发器组成的移位寄存器和异或门组成的相关模，两个加法器）的定义，让我们看一个卷积编码器的速度1 / 2的图片基本组成部分时，K = 3，m = 2时的代码： In this encoder, data bits are provided at a rate of k bits per second.在这种编码器，数据位提供了每秒k比特率。 Channel symbols are output at a rate of n = 2k symbols per second.频道符号正处于= 2K的符号每秒施氮量的输出。 The input bit is stable during the encoder cycle.输入位编码器中是稳定的周期。 The encoder cycle starts when an input clock edge occurs.编码器周期开始时，输入时钟边沿发生。 When the input clock edge occurs, the output of the left-hand flip-flop is clocked into the right-hand flip-flop, the previous input bit is clocked into the left-hand flip-flop, and a new input bit becomes available.当输入时钟边沿发生时，左边的触发器输出到右边触发器的时钟，上一个输入位移入左侧触发器，一个新的输入位可用。 Then the outputs of the upper and lower modulo-two adders become stable.然后上下模，两个加法器的输出趋于稳定。 The output selector (SEL A/B block) cycles through two states-in the first state, it selects and outputs the output of the upper modulo-two adder; in the second state, it selects and outputs the output of the lower modulo-two adder.输出选择器（sel的的A / B座）循环通过两个国家中的第一个州，它选择并输出上模，两个加法器的输出，在第二个状态，选择及输出的低模输出两个加法器。 The encoder shown above encodes the K = 3, (7, 5) convolutional code.上面的编码显示的K = 3，（7，5）卷积码编码器。 The octal numbers 7 and 5 represent the code generator polynomials, which when read in binary (111 2 and 101 2 ) correspond to the shift register connections to the upper and lower modulo-two adders, respectively.八进制数的第7和第5代表的代码生成多项式，当它在读取二进制（111 2 101 2）对应到移位寄存器的连接上，下模，两个加法器，分别为。 This code has been determined to be the best code for rate 1/2, K = 3.此代码已被确定为费率1 / 2时，K = 3的“最佳”的代码。 It is the code I will use for the remaining discussion and examples, for reasons that will become readily apparent when we get into the Viterbi decoder algorithm.这是代码，我会用余下的讨论和例子的原因很明显，这将成为我们进入时，维特比解码算法得到。 Lets look at an example input data stream, and the corresponding output data stream:让我们来看一个例子输入数据流，以及相应的输出数据流： Let the input sequence be 010111001010001 2 .让输入序列是010111001010001 2。 Assume that the outputs of both of the flip-flops in the shift register are initially cleared, ie their outputs are zeroes.假设的倒装移位寄存器中的触发器输出最初都被清除，即它们的输出是零。 The first clock cycle makes the first input bit, a zero, available to the encoder.第一个时钟周期，使第一个输入位，零，提供给编码器。 The flip-flop outputs are both zeroes.触发器的输出均为零。 The inputs to the modulo-two adders are all zeroes, so the output of the encoder is 00 2 .该加法器输入到模个都是零，所以编码器的输出为00 2。 The second clock cycle makes the second input bit available to the encoder.第二个时钟周期，使第二个输入位提供给编码器。 The left-hand flip-flop clocks in the previous bit, which was a zero, and the right-hand flip-flop clocks in the zero output by the left-hand flip-flop.左手在前面一点，这是一个零触发器首饰，钟表及右手按在左手触发器输出零触发器的时钟。 The inputs to the top modulo-two adder are 100 2 , so the output is a one.加法器输入到顶部模，两个是100 2，因此输出是一个。 The inputs to the bottom modulo-two adder are 10 2 , so the output is also a one.加法器的输入模的底部，两个10 2，因此输出也是一个。 So the encoder outputs 11 2 for the channel symbols.因此，编码器输出11个符号2的通道。 The third clock cycle makes the third input bit, a zero, available to the encoder.第三个时钟周期，使第三个输入位，一个零，可用于编码器。 The left-hand flip-flop clocks in the previous bit, which was a one, and the right-hand flip-flop clocks in the zero from two bit-times ago.左手在前面一点，这是一个触发器的时钟，而右手在零触发器时钟从两个位时代以前。 The inputs to the top modulo-two adder are 010 2 , so the output is a one.加法器输入到顶部模，两个是010 2，因此输出是一个。 The inputs to the bottom modulo-two adder are 00 2 , so the output is zero.加法器的输入模的底部，两个00 2，因此输出为零。 So the encoder outputs 10 2 for the channel symbols.因此，编码器输出10符号的通道。The timing diagram shown below illustrates the process:时序图所示说明了此过程： After all of the inputs have been presented to the encoder, the output sequence will be:输入后，所有已提交的编码器，输出序列是： 00 11 10 00 01 10 01 11 11 10 00 10 11 00 11 2 .00 11 10 00 01 10 01 11 11 10 00 10 11 00 11 2。 You can see from the structure of the rate 1/2 K = 3 convolutional encoder and from the example given above that each input bit has an effect on three successive pairs of output symbols.你可以看到从速度1 / 2 = 3的卷积编码器K表结构，由上述每个输入位有符号的三个连续对输出的影响所举的例子。 That is an extremely important point and that is what gives the convolutional code its error-correcting power.这是一个非常重要的一点，是什么给了卷积码的纠错能力。 The reason why will become evident when we get into the Viterbi decoder algorithm.之所以会成为显而易见的，当我们进入维特比解码算法得到的。 Now if we are only going to send the 15 data bits given above, in order for the last bit to affect three pairs of output symbols, we need to output two more pairs of symbols.现在，如果我们只是要为最后一位传送数据，以上述的15位，影响三种输出符号对，我们需要输出两个符号多对。 This is accomplished in our example encoder by clocking the convolutional encoder flip-flops two ( = m) more times, while holding the input at zero.这是在我们的例子编码器实现由时钟卷积编码器触发器二（=米）次以上，同时举行为零的投入。 This is called flushing the encoder, and results in two more pairs of output symbols.这就是所谓的“冲”的编码器，并在两个以上的输出符号对结果。 The final binary output of the encoder is thus 00 11 10 00 01 10 01 11 11 10 00 10 11 00 11 10 11 2 .最后二进制编码器输出的是这样00 11 10 00 01 10 01 11 11 10 00 10 11 00 11 10 11 2。 If we dont perform the flushing operation, the last m bits of the message have less error-correction capability than the first through (m - 1)th bits had.如果我们不执行冲洗操作，邮件的最后一个M位较少的纠错能力比第一至（m - 1）个位了。 This is a pretty important thing to remember if youre going to use this FEC technique in a burst-mode environment.这是一个非常重要的事情要记住，如果你要使用在突发模式环境中，本纠错技术。 Sos the step of clearing the shift register at the beginning of each burst. So的的清理移位寄存器在每个突发最初的一步。 The encoder must start in a known state and end in a known state for the decoder to be able to reconstruct the input data sequence properly.编码器必须启动一个已知状态解码器能够对输入的数据序列重建在一个已知的正常状态和结束。 Now, lets look at the encoder from another perspective.现在，让我们来看看从另一个角度编码器。 You can think of the encoder as a simple state machine.你可以认为，作为一个简单的状态机的编码器。 The example encoder has two bits of memory, so there are four possible states.这个例子编码器有两个内存位，所以有四种可能的状态。 Lets give the left-hand flip-flop a binary weight of 2 1 , and the right-hand flip-flop a binary weight of 2 0 .让我们给左边的触发器2 1二进制重量，而右手触发器2 0二进制重量。 Initially, the encoder is in the all-zeroes state.最初，该编码器在全零状态。 If the first input bit is a zero, the encoder stays in the all zeroes state at the next clock edge.如果第一个输入位是零，编码器停留在下一时钟沿在全零状态。 But if the input bit is a one, the encoder transitions to the 10 2 state at the next clock edge.