FPGA时分秒电子钟24小时计

设计一个具有时、分、秒计时的电子钟，按24小时计时。要求：（1）数字钟的时间用六位数码管分别显示时、分、秒；（2）用两个控制键，对数字钟分别进行分、时校正；（3）用Verilog HDL语言设计，用Modelsim软件做功能仿真，用Quartus II综合。（4）将设计代码和仿真代码写在作业本上。module countersmh(out,sel,dp,clock_128,clear,corr_min,corr_hour); input clock_128,clear,corr_min,corr_hour; output 6:0 out; output 2:0 sel; output dp; reg 6:0 out; reg 2:0 sel; reg 3:0 cnt_sl,cnt_sh,cnt_ml,cnt_mh,cnt_hl,cnt_hh,count; reg 15:0 fenping; wire clock_1=fenping1; always (posedge clock_128 or negedge clear) begin if (!clear) fenping = 16b0; else fenping = fenping + 1; end /cnt_sl always(posedge clock_1 or negedge clear) begin if(!clear) cnt_sl=4b0; else if (cnt_sl = 9) cnt_sl=4b0; else cnt_sl=cnt_sl+1; end /cnt_sh always(posedge clock_1 or negedge clear) begin if(!clear) cnt_sh=4b0; else if (cnt_sh = 5 & cnt_sl = 9) cnt_sh=4b0; else if (cnt_sl = 9) cnt_sh=cnt_sh+1; else cnt_sh = cnt_sh; end /cnt_ml always(posedge clock_1 or negedge clear) begin if(!clear) cnt_ml=4b0; else if (cnt_sh = 5 & cnt_sl = 9 & cnt_ml = 9) cnt_ml=4b0; else if (corr_min = 0) begin if(cnt_ml = 9) cnt_ml=4b0; else cnt_ml=cnt_ml+1; end else if (cnt_sh = 5 & cnt_sl = 9) cnt_ml=cnt_ml+1; else cnt_ml = cnt_ml; end /cnt_mh always(posedge clock_1 or negedge clear) begin if(!clear) cnt_mh=4b0; else if (cnt_sh = 5 & cnt_sl = 9 & cnt_ml = 9 & cnt_mh = 5) cnt_mh=4b0; else if (corr_min = 0) begin if(cnt_mh = 5 & cnt_ml = 9) cnt_mh=4b0; else if(cnt_ml = 9) cnt_mh=cnt_mh+1; else cnt_mh = cnt_mh; end else if (cnt_sh = 5 & cnt_sl = 9 & cnt_ml = 9) cnt_mh=cnt_mh+1; else cnt_mh = cnt_mh; end /cnt_hl always(posedge clock_1 or negedge clear) begin if(!clear) cnt_hl=4b0; else if ( cnt_hh = 2 & cnt_hl = 3 & cnt_mh = 5 & cnt_ml = 9 & cnt_sh = 5 & cnt_sl = 9 ) cnt_hl=4b0; else if ( cnt_hl = 9 & cnt_mh = 5 & cnt_ml = 9 & cnt_sh = 5 & cnt_sl = 9 ) cnt_hl=4b0; else if (corr_hour = 0) begin if(cnt_hh = 2 & cnt_hl = 3) cnt_hl=4b0; else if(cnt_hl = 9) cnt_hl=4b0; else cnt_hl=cnt_hl+1; end else if (cnt_mh = 5 & cnt_ml = 9 & cnt_sh = 5 & cnt_sl = 9) cnt_hl=cnt_hl+1; else cnt_hl = cnt_hl; end /cnt_hh always(posedge clock_1 or negedge clear) begin if(!clear) cnt_hh=4b0; else if ( cnt_hh = 2 & cnt_hl = 3 & cnt_mh = 5 & cnt_ml = 9 & cnt_sh = 5 & cnt_sl = 9 ) cnt_hh=4b0; else if (corr_hour = 0) begin if(cnt_hh = 2 & cnt_hl = 3) cnt_hh=4b0; else if (cnt_hl = 9) cnt_hh = cnt_hh+1; else cnt_hh = cnt_hh; end else if (cnt_hl = 9 & cnt_mh = 5 & cnt_ml = 9 & cnt_sh = 5 & cnt_sl = 9) cnt_hh=cnt_hh+1; else cnt_hh = cnt_hh; end /sel always(posedge clock_128 or negedge clear ) begin if(!clear) sel=0; else if(sel=3b101) sel = 3b000; else sel = sel+1; end always (sel) begin case(sel) 3b000: count=cnt_hh; 3b001: count=cnt_hl; 3b010: count=cnt_mh; 3b011: count=cnt_ml; 3b100: count=cnt_sh; 3b101: count=cnt_sl; default: count=0; endcase end /decoder wire dp; assign dp = (sel = 3b011 | sel = 3b001)?1b1:1b0; always (count) begin case(count) 4d0: out=7b011_1111; 4d1: out=7b000_0110; 4d2: out=7b101_1011; 4d3: out=7b100_1111; 4d4: out=7b110_0110; 4d5: out=7b110_1101; 4d6: out=7b111_1101; 4d7: out=7b000_0111; 4d8: out=7b111_1111; 4d9: out=7b110_1111; default: out=7b000_0000; endcase end endmoduletimescale 1ns/1nsinclude./countersmh.v module test; reg Clock_128,Clear,Corr_min,Corr_hour; wire 6:0 Out; wire 2:0 Sel; wire Dp; initial begin Clock_128=0; Clear=1; Corr_min=1; Corr_hour=1; #50 Clear=0; #50 Clear=1; #1000 Corr_min=0; #1000 Corr_min=1; #100 Corr_hour=0; #1000