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STRUCTUREANDFUNCTIONOFTHEMCS51SERIESSTRUCTUREANDFUNCTIONOFTHEMCS51SERIESONECHIPCOMPUTERISANAMEOFAPIECEOFONECHIPCOMPUTERSERIESWHICHINTELCOMPANYPRODUCESTHISCOMPANYINTRODUCED8TOPGRADEONECHIPCOMPUTERSOFMCS51SERIESIN1980AFTERINTRODUCING8ONECHIPCOMPUTERSOFMCS48SERIESIN1976ITBELONGTOALOTOFKINDSTHISLINEOFONECHIPCOMPUTERTHECHIPSHAVE,SUCHAS8051,8031,8751,80C51BH,80C31BH,ETC,THEIRBASICCOMPOSITION,BASICPERFORMANCEANDINSTRUCTIONSYSTEMAREALLTHESAME8051DAILYREPRESENTATIVES51SERIALONECHIPCOMPUTERSANONECHIPCOMPUTERSYSTEMISMADEUPOFSEVERALFOLLOWINGPARTS1ONEMICROPROCESSOROF8CPU2ATSLICEDATAMEMORYRAM128B/256B,ITUSENOTDEPOSITTINGNOTCANREADING/DATATHATWRITE,SUCHASRESULTNOTMIDDLEOFOPERATION,FINALRESULTANDDATAWANTEDTOSHOW,ETC3PROCEDUREMEMORYROM/EPROM4KB/8KB,ISUSEDTOPRESERVETHEPROCEDURE,SOMEINITIALDATAANDFORMINSLICEBUTDOESNOTTAKEROM/EPROMWITHINSOMEONECHIPCOMPUTERS,SUCHAS8031,8032,80C,ETC4FOUR8RUNSIDEBYSIDEI/OINTERFACEP0FOURP3,EACHMOUTHCANUSEASINTRODUCTION,MAYUSEASEXPORTINGTOO5TWOTIMER/COUNTER,EACHTIMER/COUNTERMAYSETUPANDCOUNTINTHEWAY,USEDTOCOUNTTOTHEEXTERNALINCIDENT,CANSETUPINTOATIMINGWAYTOO,ANDCANACCORDINGTOCOUNTORRESULTOFTIMINGREALIZETHECONTROLOFTHECOMPUTER6FIVECUTOFFCUTTINGOFFTHECONTROLSYSTEMOFTHESOURCE7ONEALLDUPLEXINGSERIALI/OMOUTHOFUARTUNIVERSALASYNCHRONOUSRECEIVER/TRANSMITTERUART,ISITREALIZEONECHIPCOMPUTERORONECHIPCOMPUTERANDSERIALCOMMUNICATIONOFCOMPUTERTOUSEFOR8STRETCHOSCILLATORANDCLOCKPRODUCECIRCUIT,QUARTZCRYSTALFINELYTUNEELECTRICCAPACITYNEEDOUTERALLOWOSCILLATIONFREQUENCYAS12MEGAHERTASNOWATMOSTEVERYTHEABOVEMENTIONEDPARTWASJOINEDTHROUGHTHEINSIDEDATABUSAMONGTHEM,CPUISACOREOFTHEONECHIPCOMPUTER,ITISTHECONTROLOFTHECOMPUTERANDCOMMANDCENTRE,MADEUPOFSUCHPARTSASARITHMETICUNITANDCONTROLLER,ETCTHEARITHMETICUNITCANCARRYON8PERSONSOFARITHMETICOPERATIONANDUNITALUOFLOGICOPERATIONWHILEINCLUDINGONE,THE1STORINGDEVICETEMPORARILIESOF8,STORINGDEVICE2TEMPORARILY,8SACCUMULATIONDEVICEACC,REGISTERBANDPROCEDURESTATEREGISTERPSW,ETCPERSONWHOACCUMULATEACCCOUNTBY2INPUTENDSENTEREDOFCHECKINGETCTEMPORARILYASONEOPERATIONOFTEN,COMEFROMPERSONWHOSTORE1OPERATIONISITISITMAKEOPERATIONTOGOONTOCOUNTTEMPORARILY,OPERATIONRESULTANDLOOPBACKACCWITHANOTHERONEINADDITION,ACCISOFTENREGARDEDASTHETRANSFERSTATIONOFDATATRANSMISSIONON8051INSIDETHESAMEASGENERALMICROPROCESSOR,ITISTHEBUSIESTREGISTERHELPREMEMBERINGTHATAGREEINGWITHAEXPRESSESINTHEORDERTHECONTROLLERINCLUDESTHEPROCEDURECOUNTER,THEORDERISDEPOSITTED,THEORDERDECIPHER,THEOSCILLATORANDTIMINGCIRCUIT,ETCTHEPROCEDURECOUNTERISMADEUPOFCOUNTEROF8FORTWO,AMOUNTSTO16ITISABYTEADDRESSCOUNTEROFTHEPROCEDUREINFACT,THECONTENTISTHENEXTIATHATWILLCARRIEDOUTINPCTHECONTENTWHICHCHANGESITCANCHANGETHEDIRECTIONTHATTHEPROCEDURECARRIESOUTSHAKETHECIRCUITIN8051ONECHIPCOMPUTERS,ONLYNEEDOUTERQUARTZCRYSTALANDFREQUENCYTOFINELYTUNETHEELECTRICCAPACITY,ITSFREQUENCYRANGEISITS12MHZOF12MHZTHISPULSESIGNAL,AS8051BASICBEATSOFWORKING,NAMELYTHEMINIMUMUNITOFTIME8051ISTHESAMEASOTHERCOMPUTERS,THEWORKINHARMONYUNDERTHECONTROLOFTHEBASICBEAT,JUSTLIKEANORCHESTRAACCORDINGTOTHEBEATPLAYTHATISCOMMANDEDTHEREAREROMPROCEDUREMEMORY,CANONLYREADANDRAMIN8051SLICESDATAMEMORY,CANISITCANWRITETWOTOREAD,THEYHAVEEACHINDEPENDENTMEMORYADDRESSSPACE,DISPOSEWAYTOBETHESAMEWITHGENERALMEMORYOFCOMPUTERPROCEDURE8051MEMORYAND8751SLICEPROCEDUREMEMORYCAPACITY4KB,ADDRESSBEGINFROM0000H,USEDFORPRESERVINGTHEPROCEDUREANDFORMCONSTANTDATA805187518031OFMEMORYDATAMEMORY128B,ADDRESSFALSE00FH,USEFORMIDDLERESULTTODEPOSITOPERATION,THEDATAARESTOREDTEMPORARILYANDTHEDATAAREBUFFEREDETCINRAMOFTHIS128B,THEREISUNITOF32BYTESESTHATCANBEAPPOINTEDASTHEJOBREGISTER,THISANDGENERALMICROPROCESSORISDIFFERENT,8051SLICERAMANDJOBREGISTERRANKONEFORMATIONTHESAMETOARRANGETHELOCATIONITISNOTVERYTHESAMETHATTHEMEMORYOFMCS51SERIESONECHIPCOMPUTERANDGENERALCOMPUTERDISPOSESTHEWAYINADDITIONGENERALCOMPUTERFORFIRSTADDRESSSPACE,ROMANDRAMCANARRANGEINDIFFERENTSPACEWITHINTHERANGEOFTHISADDRESSATWILL,NAMELYTHEADDRESSESOFROMANDRAM,WITHDISTRIBUTINGDIFFERENTADDRESSSPACEINAFORMATIONWHILEVISITINGTHEMEMORY,CORRESPONDINGANDONLYANADDRESSMEMORYUNIT,CANROM,ITCANBERAMTOO,ANDBYVISITINGTHEORDERSIMILARLYTHISKINDOFMEMORYSTRUCTUREISCALLEDTHESTRUCTUREOFPRINCETON8051MEMORIESAREDIVIDEDINTOPROCEDUREMEMORYSPACEANDDATAMEMORYSPACEONTHEPHYSICSSTRUCTURE,THEREAREFOURMEMORYSPACESINALLTHEPROCEDURESTORESINONEANDDATAMEMORYSPACEOUTSIDEDATAMEMORYANDONEINPROCEDUREMEMORYSPACEANDONEOUTSIDEONE,THESTRUCTUREFORMSOFTHISKINDOFPROCEDUREDEVICEANDDATAMEMORYSEPARATEDFORMDATAMEMORY,CALLEDHARVARDSTRUCTUREBUTUSETHEANGLEFROMUSERS,8051MEMORYADDRESSSPACEISDIVIDEDINTOTHREEKINDS1INTHESLICE,ARRANGEBLOCKSOFFFFFH,0000HOFLOCATION,INUNISONOUTSIDETHESLICEUSE16ADDRESSES2THEDATAMEMORYADDRESSSPACEOUTSIDEONEOF64KB,THEADDRESSISARRANGEDFROM0000H64KBFFFFHWITH16ADDRESSESTOOTOTHELOCATION3DATAMEMORYADDRESSSPACEOF256BUSE8ADDRESSESTHREEABOVEMENTIONEDMEMORYSPACEADDRESSESOVERLAP,FORDISTINGUISHINGANDDESIGNINGTHEORDERSYMBOLOFDIFFERENTDATATRANSMISSIONINTHEINSTRUCTIONSYSTEMOF8051CPUVISITSLICE,ROMORDERSPENDMOVC,VISITBLOCKRAMORDERUSESMOVXOUTSIDETHESLICE,RAMORDERUSESMOVTOVISITINSLICE8051ONECHIPCOMPUTERHAVEFOUR8WALKABREASTI/OPORT,CALLP0,P1,P2ANDP3EACHPORTIS8ACCURATETWOWAYMOUTHS,ACCOUNTSFOR32PINSALTOGETHEREVERYONEI/OLINECANBEUSEDASINTRODUCTIONANDEXPORTEDINDEPENDENTLYEACHPORTINCLUDESALATCHNAMELYSPECIALFUNCTIONREGISTER,ONEEXPORTSTHEDRIVERANDAINTRODUCTIONBUFFERMAKEDATACANLATCHWHENOUTPUTTING,DATACANBUFFERWHENMAKINGINTRODUCTION,BUTFOURFUNCTIONOFPASSWAYTHESESELFSAMEEXPANDAMONGTHESYSTEMOFMEMORYOUTSIDEHAVINGSLICE,FOURPORTTHESEMAYSERVEASACCURATETWOWAYMOUTHOFI/OINCOMMONUSEEXPANDAMONGTHESYSTEMOFMEMORYOUTSIDEHAVINGSLICE,P2MOUTHSEEHIGH8ADDRESSOFFP0MOUTHISATWOWAYBUS,SENDTHEINTRODUCTIONOF8LOWADDRESSESANDDATA/EXPORTINTIMESHARINGTHECIRCUITOF8051ONECHIPCOMPUTERSANDFOURI/OPORTSISVERYINGENIOUSINDESIGNFAMILIARWITHI/OPORTLOGICALCIRCUIT,NOTONLYHELPTOUSEPORTSCORRECTLYANDRATIONALLY,ANDWILLINSPIRETODESIGNINGTHEPERIPHERALLOGICALCIRCUITOFONECHIPCOMPUTERTOSOMEEXTENTLOADABILITYANDINTERFACEOFPORTHAVECERTAINREQUIREMENT,BECAUSEOUTPUTGRADE,P0OFMOUTHANDP1ENDOUTPUT,P3OFMOUTHGRADEDIFFERENTATSTRUCTURE,SO,THELOADABILITYANDINTERFACEOFITSDOORDEMANDTOHAVENOTHINGINCOMMONWITHEACHOTHERP0MOUTHISDIFFERENTFROMOTHERMOUTHS,ITSOUTPUTGRADEDRAWSTHERESISTANCESUPREMLYWHENUSINGITASTHEMOUTHINCOMMONUSETOUSE,OUTPUTGRADEISITLEAKCIRCUITTOTURNON,ISITISITURGENMOSDRAWTHERESISTANCEONTAKINGTOBEOUTERWITHITWHILEINPUTTINGTOGOOUTTOFAILWHENBEINGUSEDASINTRODUCTION,SHOULDWRITE“1“TOALATCHFIRSTEVERYONEWITHP0MOUTHCANDRIVE8MODELLSTTLLOADTOEXPORTP1MOUTHISANACCURATETWOWAYMOUTHTOO,USEDASI/OINCOMMONUSEDIFFERENTFROMP0MOUTHOUTPUTOFCIRCUITITS,DRAWLOADRESISTANCELINKWITHPOWERONINSIDEHAVEINFACT,THERESISTANCEISTHATTWOEFFECTSAREINCHARGEOFFETANDTOGETHERONEFETISINCHARGEOFLOAD,ITSRESISTANCEISREGULARANOTHERONECANISITLEADTOWORKWITHCLOSEATTWOSTATE,MAKEITSPRESIDENTRESISTANCEVALUECHANGEAPPROXIMATE0ORGROUPVALUEHEAVYTWOSITUATIONVERYWHENITIS0THATTHERESISTANCEISAPPROXIMATE,CANDRAWTHEPINTOTHEHIGHLEVELFASTWHENRESISTANCEVALUEISVERYLARGE,P1MOUTH,INORDERTOHINDERTHEINTRODUCTIONSTATEHIGHOUTPUTASP1MOUTHHIGHELECTRICITYATORDINARYTIMES,CANISITDRAWELECTRICCURRENTLOADTOOFFEROUTWARDS,DRAWTHERESISTANCEONNEEDNTANSWERANDTHENNINGHEREWHENTHEPORTISUSEDASINTRODUCTION,MUSTWRITEINTO1TOTHECORRESPONDINGLATCHFIRSTTOO,MAKEFETENDRELATIVELYABOUT20,000OHMSBECAUSEOFTHELOADRESISTANCEINSCENEANDBECAUSE40,000OHMS,WILLNOTEXERTANINFLUENCEONTHEDATATHATAREINPUTTHESTRUCTUREOFP2SOMEMOUTHISSIMILARTOP0MOUTH,THEREAREMUXSWITCHESISITSIMILARTOMOUTHPARTLYTOURGE,BUTMOUTHLARGEACONVERSIONCONTROLSSOMETHANP1P3MOUTHONEMULTIFUNCTIONALPORT,MOUTHGETTINGMANYTHANP1ITHAVE“AND“3DOORAND4BUFFER“TWOPARTTHESE,MAKEHERBESIDESACCURATETWOWAYFUNCTIONWITHP1MOUTHJUST,CANALSOUSETHESECONDFUNCTIONOFEVERYPIN,“AND“DOOR3FUNCTIONONESWITCHINFACT,ITDETERMINESTOBETOOUTPUTDATAOFLATCHTOOUTPUTSECONDSIGNALOFFUNCTIONACTASWAT1OCLOCK,OUTPUTQENDSIGNALACTASQAT1OCLOCK,CANOUTPUTWLINESIGNALATTHETIMEOFPROGRAMMING,ITISTHATTHEFIRSTFUNCTIONISSTILLTHESECONDFUNCTIONBUTNEEDNTHAVESOFTWARETHATSETUPP3MOUTHINADVANCEITHARDWARENOTINSIDEISTHEAUTOMATICTOHAVETWOFUNCTIONOUTPUTTEDWHENCPUCARRIESONSFRANDSEEKSTHELOCATIONTHELOCATIONORTHEBYTETOVISITTOP3MOUTH/ATNOTLASTINGLINING,THEREAREINSIDEHARDWARELATCHQS1THEOPERATIONPRINCIPLEOFP3MOUTHISSIMILARTOP1MOUTHOUTPUTGRADE,P3OFMOUTH,P1OFP1,CONNECTWITHINSIDEHAVELOADRESISTANCEOFDRAWING,EVERYONEOFTHEYCANDRIVE4MODELLSTTLLOADTOOUTPUTASWHILEINPUTTINGTHEMOUTH,ANYTTLORNMOSCIRCUITCANDRIVEP1OF8051ONECHIPCOMPUTERSASP3MOUTHINANORMALWAYBECAUSEDRAWRESISTANCEONOUTPUTGRADEOFTHEMHAVE,CANOPENAWAYCOLLECTORTOOORDRAINSOURCERESISTANCEISITURGETOOPENAWAY,DONOTNEEDTOHAVETHERESISTANCEOFDRAWINGOUTERLYMOUTHSAREALLACCURATETWOWAYMOUTHSTOOWHENTHECONDUCTISINPUT,MUSTWRITETHECORRESPONDINGPORTLATCHWITH1FIRSTASTO80C51ONECHIPCOMPUTER,PORTCANONLYOFFERMILLIAMPEREOFOUTPUTELECTRICCURRENTS,ISITOUTPUTMOUTHGOWHENURGINGONEORDINARYBASINGOFTRANSISTORTOREGARDAS,SHOULDCONTACTARESISTANCEAMONGTHEPORTANDTRANSISTORBASE,INORDERTOTHEELECTRICITYWHILERESTRAININGTHEHIGHLEVELFROMEXPORTINGP1P3BEINGRESTOREDTOTHETHRONEISTHEOPERATIONOFINITIALIZINGOFANONECHIPCOMPUTERITSMAINFUNCTIONISTOTURNPCINTO0000HINITIALLY,MAKETHEONECHIPCOMPUTERBEGINTOHOLDTHECONDUCTPROCEDUREFROMUNIT0000HEXCEPTTHATTHEONESTHATENTERTHESYSTEMAREINITIALIZEDNORMALLY,ASBECAUSEPROCEDUREOPERATEITMAKEMISTAKESOROPERATETHEREARENTMISTAKE,INORDERTOEXTRICATEONESELFFROMAPREDICAMENT,NEEDTOBEPRESSEDANDRESTOREDTOTHETHRONETHEKEYRESTARTINGTOOITISANINPUTENDWHICHISRESTOREDTOTHETHRONETHESIGNALIN8051CHINARSTPINRESTORETOTHETHRONESIGNALHIGHLEVELEFFECTIVE,SHOULDSUSTAIN24SHAKECYCLENAMELY2MACHINECYCLESTHEABOVEITSEFFECTIVETIMESIF6OFFREQUENCYOFUTILIZATIONBRILLIANTTOSHAKE,RESTORETOTHETHRONESIGNALDURATIONSHOULDEXCEED4DELICATETOFINISHRESTORINGTOTHETHRONEANDOPERATINGPRODUCETHELOGICPICTUREOFCIRCUITWHICHISRESTOREDTOTHETHRONETHESIGNALRESTORETOTHETHRONETHECIRCUITANDINCLUDETWOPARTSOUTSIDEINTHECHIPENTIRELYOUTSIDETHATCIRCUITPRODUCETORESTORETOTHETHRONESIGNALRSTHANDOVERTOSCHMITTSTRIGGER,RESTORETOTHETHRONECIRCUITSAMPLETOOUTPUT,SCHMITTOFTRIGGERCONSTANTLYINEACHS5P2,MACHINEOFCYCLEINHAVINGONEMORE,THENJUSTGOTANDRESTOREDTOTHETHRONEANDOPERATEDTHENECESSARYSIGNALINSIDLYRESTORETOTHETHRONERESISTANCEOFCIRCUITGENERALLY,ELECTRICCAPACITYPARAMETERSUITABLEFOR6BRILLIANTTOSHAKE,CANISITRESTORETOTHETHRONESIGNALHIGHLEVELDURATIONGREATERTHAN2MACHINECYCLESTOGUARANTEEBEINGRESTOREDTOTHETHRONEINTHECIRCUITISSIMPLE,ITSFUNCTIONISVERYIMPORTANTPIECESOFONECHIPCOMPUTERSYSTEMCOULDNORMALRUNNING,SHOULDFIRSTCHECKITCANRESTORETOTHETHRONENOTSUCCEEDINGCHECKINGANDCANPOPONESHEADANDMONITORTHEPINWITHTHEOSCILLOGRAPHTENTATIVELY,PUSHANDISRESTOREDTOTHETHRONETHEKEY,THEWAVEFORMTHATOBSERVESANDHASENOUGHRANGEISEXPORTEDINSTANTANEOUS,CANALSOTHROUGHISITRESTORETOTHETHRONECIRCUITGROUPHOLDINGVALUECARRYONTHEEXPERIMENTTOCHANGE中文翻译51系列单片机的功能和结构MCS51系列单片机具有一个单芯片电脑的结构和功能,它是英特尔公司生产的系列产品的名称。这家公司在1976年推出后,引进8位单芯片的MCS48系列计算机后于1980年推出的8位的MCS51系列单芯片计算机。诸如此类的单芯片电脑有很多种,如8051,8031,8751,80C51BH,80C31BH等,其基本组成,基本性能和指令系统都是相同的。8051是51系列单芯片电脑的代表。一个单芯片的计算机系统由以下几个部分组成(1)一个8位的微处理器(CPU)。(2)片内数据存储器RAM(128B/256B),它只读/写数据,如结果不在操作过程中,最终结果要显示数据(3)程序存储器ROM/EPROM(4KB/8KB),是用来保存程序,一些初步的数据和切片的形式。但一些单芯片电脑没有考虑ROM/EPROM,如8031,8032,80C51等等。(4)4个8路运行的I/O接口,P0,P1,P2,P3,每口可以用作入口,也可以用作出口。(5)两个定时/计数器,每个定时/计数器可设置和计数的方式,用来计数外部事件,可以设置成定时方式也可以根据计算结果或定时控制实现计算机。(6)5个中断(7)一个全双工串行的I/UART(通用异步接收器I口/发送器(UART),它是实现单芯片电脑或单芯片计算机和计算机的串行通信使用。(8)振荡器和时钟产生电路,需要考虑石英晶体微调能力。允许振荡频率为12MHZ,每一个上述的部分都是通过内部数据总线连接。其中CPU是一个芯片计算机的核心,它是计算机的指挥中心,是由算术单元和控制器等部分组成。算术单元可以进行8位算术运算和逻辑运算,ALU单元是其中一种运算器,18个存储设备,暂存设备的积累设备进行协调,程序状态寄存器PSW积累了2个输入端的计数等检查暂时作为一个操作往往由人来操作谁储存1输入的是它使操作去上暂时计数,另有一个操作的结果,回环协调。此外,协调往往是作为对8051内的数据传输转运站考虑。作为一般的微处理器,它是最繁忙的,帮助记住和同意与其的顺序表示。该控制器包括程序计数器,解密的顺序。振荡器和定时电路等的程序计数器是一个由8个计数器为2,总计16位。这是一个字节的地址,其实程序计数器,是将在个人电脑内进行。从而改变它的内容可以改变方向的程序进行。在8051的单芯片电脑中的电路,只需要外部石英晶体和频率微调电容,其频率范围为12MHZ的其12MHZ的。这种脉冲信号,作为8051的工作,即单位时间的最低基本节奏。8051是其他电脑一样,在拍控制的基本工作在和谐,就像一个管弦乐队,根据击败发挥是指挥。有光盘(程序存储器,只能读取),并在8051片(数据存储器RAM,可以是可写可读,他们各自独立的内存地址空间,处理办法是,与一般的电脑记忆体相同。8051和8751的程序存储器的存储容量4KB的程序切片,地址开始从0000H开始执行,维护的程序和形式不断使用。数据80518751的内存数据存储器128B条8031,地址虚假00FH,中层结果存入操作使用,数据存储和数据是暂时缓冲等。在这128B条内存,有32字节,可以作为工作寄存器使用,这和一般的微处理器是不同的,8051片RAM和登记形成的同一级到安排的位置。这不是很相同的,MCS51系列内存的单芯片计算机和通用计算机作主除了道路。通用计算机的第一个地址空间,ROM和RAM,可安排在不同的空间在这个范围内的地址范围,即ROM和RAM地址的形成与分布在不同的地址空间。在访问内存,相应的,只有一个地址的内存单元,可以用外部存储,也可以内存,并通过访问顺序与此类似。这种内存结构的一种被称为普林斯顿结构。8051记忆分为程序存储器空间和数据存储空间的物理结构上划分,有四个在所有的记忆体空间在1和数据外部数据存储器和程序存储器空间之一,一组在外面一个内存空间的程序商店,结构这一种形式的程序和数据存储器器件数据存储器分开的形式,称为哈佛结构。但是,从用户使用,8051的内存地址空间分为三种分为(1)片内,(使用16个地址一致的FFFFH,地点为0000H,块)。(2)64KB的外部数据存储器空间的一个地址,该地址是从0000H开始执行64KB的FFFFH安排16地址,也到该位置。(3)数据存储器的256B(使用8个地址)的地址空间。上述三个内存空间的地址重叠,区分和设计的8051指令系统中不同的数据传输顺序代码CPU的访问片,访问RAM块顺序使用MOVX指令外片,内存为访问片。8051单芯片的电脑有4个8步行并进的I/O端口,分别为P0,P1,P2和P3。每个端口8位的双向口,共占了32针。每一个I/O线可作为独立的入口和出口。每个端口包括一个锁存器(即特殊功能寄存器),1名入口和1出口引进缓冲区。使数据能锁存输出时,数据缓冲区时,可以引进,但4个通道这些自我相同的功能。系统中的内存片展开外来的,这四个港口可作为准确的双向的I/共同使用输出口。系统的内存中展开外来的片,P2口处于高位,8地址关闭入口P0口是双向总线,发送地址和8个低数据。8051单芯片电脑的4个I/O端口是非常巧妙的电路设计。熟悉I/O端口的逻辑电路,不仅有助于正确和合理利用端口,并在一定程度上将有助于设计周边的单芯片计算机的逻辑电路。在一定程度上负载能力和端口界面有一定的要求,因为输出级,和P1口输出端,P3口与P0口结构的不同,因此,负载能力和接口需求互相无
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