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英文原文STRUCTUREANDFUNCTIONOFTHEMCS51SERIESSTRUCTUREANDFUNCTIONOFTHEMCS51SERIESONECHIPCOMPUTERMCS51ISANAMEOFAPIECEOFONECHIPCOMPUTERSERIESWHICHINTELCOMPANYPRODUCESTHISCOMPANYINTRODUCED8TOPGRADEONECHIPCOMPUTERSOFMCS51SERIESIN1980AFTERINTRODUCING8ONECHIPCOMPUTERSOFMCS48SERIESIN1976ITBELONGTOALOTOFKINDSTHISLINEOFONECHIPCOMPUTERTHECHIPSHAVE,SUCHAS8051,8031,8751,80C51BH,80C31BH,ETC,THEIRBASICCOMPOSITION,BASICPERFORMANCEANDINSTRUCTIONSYSTEMAREALLTHESAME8051DAILYREPRESENTATIVES51SERIALONECHIPCOMPUTERSANONECHIPCOMPUTERSYSTEMISMADEUPOFSEVERALFOLLOWINGPARTS1ONEMICROPROCESSOROF8CPU2ATSLICEDATAMEMORYRAM128B/256B,ITUSENOTDEPOSITTINGNOTCANREADING/DATATHATWRITE,SUCHASRESULTNOTMIDDLEOFOPERATION,FINALRESULTANDDATAWANTEDTOSHOW,ETC3PROCEDUREMEMORYROM/EPROM4KB/8KB,ISUSEDTOPRESERVETHEPROCEDURE,SOMEINITIALDATAANDFORMINSLICEBUTDOESNOTTAKEROM/EPROMWITHINSOMEONECHIPCOMPUTERS,SUCHAS8031,8032,80C,ETC4FOUR8RUNSIDEBYSIDEI/OINTERFACEP0FOURP3,EACHMOUTHCANUSEASINTRODUCTION,MAYUSEASEXPORTINGTOO5TWOTIMER/COUNTER,EACHTIMER/COUNTERMAYSETUPANDCOUNTINTHEWAY,USEDTOCOUNTTOTHEEXTERNALINCIDENT,CANSETUPINTOATIMINGWAYTOO,ANDCANACCORDINGTOCOUNTORRESULTOFTIMINGREALIZETHECONTROLOFTHECOMPUTER6FIVECUTOFFCUTTINGOFFTHECONTROLSYSTEMOFTHESOURCE7ONEALLDUPLEXINGSERIALI/OMOUTHOFUARTUNIVERSALASYNCHRONOUSRECEIVER/TRANSMITTERUART,ISITREALIZEONECHIPCOMPUTERORONECHIPCOMPUTERANDSERIALCOMMUNICATIONOFCOMPUTERTOUSEFOR8STRETCHOSCILLATORANDCLOCKPRODUCECIRCUIT,QUARTZCRYSTALFINELYTUNEELECTRICCAPACITYNEEDOUTERALLOWOSCILLATIONFREQUENCYAS12MEGAHERTASNOWATMOSTEVERYTHEABOVEMENTIONEDPARTWASJOINEDTHROUGHTHEINSIDEDATABUSAMONGTHEM,CPUISACOREOFTHEONECHIPCOMPUTER,ITISTHECONTROLOFTHECOMPUTERANDCOMMANDCENTRE,MADEUPOFSUCHPARTSASARITHMETICUNITANDCONTROLLER,ETCTHEARITHMETICUNITCANCARRYON8PERSONSOFARITHMETICOPERATIONANDUNITALUOFLOGICOPERATIONWHILEINCLUDINGONE,THE1STORINGDEVICETEMPORARILIESOF8,STORINGDEVICE2TEMPORARILY,8SACCUMULATIONDEVICEACC,REGISTERBANDPROCEDURESTATEREGISTERPSW,ETCPERSONWHOACCUMULATEACCCOUNTBY2INPUTENDSENTEREDOFCHECKINGETCTEMPORARILYASONEOPERATIONOFTEN,COMEFROMPERSONWHOSTORE1OPERATIONISITISITMAKEOPERATIONTOGOONTOCOUNTTEMPORARILY,OPERATIONRESULTANDLOOPBACKACCWITHANOTHERONEINADDITION,ACCISOFTENREGARDEDASTHETRANSFERSTATIONOFDATATRANSMISSIONON8051INSIDETHESAMEASGENERALMICROPROCESSOR,ITISTHEBUSIESTREGISTERHELPREMEMBERINGTHATAGREEINGWITHAEXPRESSESINTHEORDERTHECONTROLLERINCLUDESTHEPROCEDURECOUNTER,THEORDERISDEPOSITTED,THEORDERDECIPHER,THEOSCILLATORANDTIMINGCIRCUIT,ETCTHEPROCEDURECOUNTERISMADEUPOFCOUNTEROF8FORTWO,AMOUNTSTO16ITISABYTEADDRESSCOUNTEROFTHEPROCEDUREINFACT,THECONTENTISTHENEXTIATHATWILLCARRIEDOUTINPCTHECONTENTWHICHCHANGESITCANCHANGETHEDIRECTIONTHATTHEPROCEDURECARRIESOUTSHAKETHECIRCUITIN8051ONECHIPCOMPUTERS,ONLYNEEDOUTERQUARTZCRYSTALANDFREQUENCYTOFINELYTUNETHEELECTRICCAPACITY,ITSFREQUENCYRANGEISITS12MHZOF12MHZTHISPULSESIGNAL,AS8051BASICBEATSOFWORKING,NAMELYTHEMINIMUMUNITOFTIME8051ISTHESAMEASOTHERCOMPUTERS,THEWORKINHARMONYUNDERTHECONTROLOFTHEBASICBEAT,JUSTLIKEANORCHESTRAACCORDINGTOTHEBEATPLAYTHATISCOMMANDEDTHEREAREROMPROCEDUREMEMORY,CANONLYREADANDRAMIN8051SLICESDATAMEMORY,CANISITCANWRITETWOTOREAD,THEYHAVEEACHINDEPENDENTMEMORYADDRESSSPACE,DISPOSEWAYTOBETHESAMEWITHGENERALMEMORYOFCOMPUTERPROCEDURE8051MEMORYAND8751SLICEPROCEDUREMEMORYCAPACITY4KB,ADDRESSBEGINFROM0000H,USEDFORPRESERVINGTHEPROCEDUREANDFORMCONSTANTDATA805187518031OFMEMORYDATAMEMORY128B,ADDRESSFALSE00FH,USEFORMIDDLERESULTTODEPOSITOPERATION,THEDATAARESTOREDTEMPORARILYANDTHEDATAAREBUFFEREDETCINRAMOFTHIS128B,THEREISUNITOF32BYTESESTHATCANBEAPPOINTEDASTHEJOBREGISTER,THISANDGENERALMICROPROCESSORISDIFFERENT,8051SLICERAMANDJOBREGISTERRANKONEFORMATIONTHESAMETOARRANGETHELOCATIONITISNOTVERYTHESAMETHATTHEMEMORYOFMCS51SERIESONECHIPCOMPUTERANDGENERALCOMPUTERDISPOSESTHEWAYINADDITIONGENERALCOMPUTERFORFIRSTADDRESSSPACE,ROMANDRAMCANARRANGEINDIFFERENTSPACEWITHINTHERANGEOFTHISADDRESSATWILL,NAMELYTHEADDRESSESOFROMANDRAM,WITHDISTRIBUTINGDIFFERENTADDRESSSPACEINAFORMATIONWHILEVISITINGTHEMEMORY,CORRESPONDINGANDONLYANADDRESSMEMORYUNIT,CANROM,ITCANBERAMTOO,ANDBYVISITINGTHEORDERSIMILARLYTHISKINDOFMEMORYSTRUCTUREISCALLEDTHESTRUCTUREOFPRINCETON8051MEMORIESAREDIVIDEDINTOPROCEDUREMEMORYSPACEANDDATAMEMORYSPACEONTHEPHYSICSSTRUCTURE,THEREAREFOURMEMORYSPACESINALLTHEPROCEDURESTORESINONEANDDATAMEMORYSPACEOUTSIDEDATAMEMORYANDONEINPROCEDUREMEMORYSPACEANDONEOUTSIDEONE,THESTRUCTUREFORMSOFTHISKINDOFPROCEDUREDEVICEANDDATAMEMORYSEPARATEDFORMDATAMEMORY,CALLEDHARVARDSTRUCTUREBUTUSETHEANGLEFROMUSERS,8051MEMORYADDRESSSPACEISDIVIDEDINTOTHREEKINDS1INTHESLICE,ARRANGEBLOCKSOFFFFFH,0000HOFLOCATION,INUNISONOUTSIDETHESLICEUSE16ADDRESSES2THEDATAMEMORYADDRESSSPACEOUTSIDEONEOF64KB,THEADDRESSISARRANGEDFROM0000H64KBFFFFHWITH16ADDRESSESTOOTOTHELOCATION3DATAMEMORYADDRESSSPACEOF256BUSE8ADDRESSESTHREEABOVEMENTIONEDMEMORYSPACEADDRESSESOVERLAP,FORDISTINGUISHINGANDDESIGNINGTHEORDERSYMBOLOFDIFFERENTDATATRANSMISSIONINTHEINSTRUCTIONSYSTEMOF8051CPUVISITSLICE,ROMORDERSPENDMOVC,VISITBLOCKRAMORDERUSESMOVXOUTSIDETHESLICE,RAMORDERUSESMOVTOVISITINSLICE8051ONECHIPCOMPUTERHAVEFOUR8WALKABREASTI/OPORT,CALLP0,P1,P2ANDP3EACHPORTIS8ACCURATETWOWAYMOUTHS,ACCOUNTSFOR32PINSALTOGETHEREVERYONEI/OLINECANBEUSEDASINTRODUCTIONANDEXPORTEDINDEPENDENTLYEACHPORTINCLUDESALATCHNAMELYSPECIALFUNCTIONREGISTER,ONEEXPORTSTHEDRIVERANDAINTRODUCTIONBUFFERMAKEDATACANLATCHWHENOUTPUTTING,DATACANBUFFERWHENMAKINGINTRODUCTION,BUTFOURFUNCTIONOFPASSWAYTHESESELFSAMEEXPANDAMONGTHESYSTEMOFMEMORYOUTSIDEHAVINGSLICE,FOURPORTTHESEMAYSERVEASACCURATETWOWAYMOUTHOFI/OINCOMMONUSEEXPANDAMONGTHESYSTEMOFMEMORYOUTSIDEHAVINGSLICE,P2MOUTHSEEHIGH8ADDRESSOFFP0MOUTHISATWOWAYBUS,SENDTHEINTRODUCTIONOF8LOWADDRESSESANDDATA/EXPORTINTIMESHARINGOUTPUTGRADE,P3OFMOUTH,P1OFP1,CONNECTWITHINSIDEHAVELOADRESISTANCEOFDRAWING,EVERYONEOFTHEYCANDRIVE4MODELLSTTLLOADTOOUTPUTASWHILEINPUTTINGTHEMOUTH,ANYTTLORNMOSCIRCUITCANDRIVEP1OF8051ONECHIPCOMPUTERSASP3MOUTHINANORMALWAYBECAUSEDRAWRESISTANCEONOUTPUTGRADEOFTHEMHAVE,CANOPENAWAYCOLLECTORTOOORDRAINSOURCERESISTANCEISITURGETOOPENAWAY,DONOTNEEDTOHAVETHERESISTANCEOFDRAWINGOUTERLYMOUTHSAREALLACCURATETWOWAYMOUTHSTOOWHENTHECONDUCTISINPUT,MUSTWRITETHECORRESPONDINGPORTLATCHWITH1FIRSTASTO80C51ONECHIPCOMPUTER,PORTCANONLYOFFERMILLIAMPEREOFOUTPUTELECTRICCURRENTS,ISITOUTPUTMOUTHGOWHENURGINGONEORDINARYBASINGOFTRANSISTORTOREGARDAS,SHOULDCONTACTARESISTANCEAMONGTHEPORTANDTRANSISTORBASE,INORDERTOTHEELECTRICITYWHILERESTRAININGTHEHIGHLEVELFROMEXPORTINGP1P3BEINGRESTOREDTOTHETHRONEISTHEOPERATIONOFINITIALIZINGOFANONECHIPCOMPUTERITSMAINFUNCTIONISTOTURNPCINTO0000HINITIALLY,MAKETHEONECHIPCOMPUTERBEGINTOHOLDTHECONDUCTPROCEDUREFROMUNIT0000HEXCEPTTHATTHEONESTHATENTERTHESYSTEMAREINITIALIZEDNORMALLY,ASBECAUSEPROCEDUREOPERATEITMAKEMISTAKESOROPERATETHEREARENTMISTAKE,INORDERTOEXTRICATEONESELFFROMAPREDICAMENT,NEEDTOBEPRESSEDANDRESTOREDTOTHETHRONETHEKEYRESTARTINGTOOITISANINPUTENDWHICHISRESTOREDTOTHETHRONETHESIGNALIN8051CHINARSTPINRESTORETOTHETHRONESIGNALHIGHLEVELEFFECTIVE,SHOULDSUSTAIN24SHAKECYCLENAMELY2MACHINECYCLESTHEABOVEITSEFFECTIVETIMESIF6OFFREQUENCYOFUTILIZATIONBRILLIANTTOSHAKE,RESTORETOTHETHRONESIGNALDURATIONSHOULDEXCEED4DELICATETOFINISHRESTORINGTOTHETHRONEANDOPERATINGPRODUCETHELOGICPICTUREOFCIRCUITWHICHISRESTOREDTOTHETHRONETHESIGNALRESTORETOTHETHRONETHECIRCUITANDINCLUDETWOPARTSOUTSIDEINTHECHIPENTIRELYOUTSIDETHATCIRCUITPRODUCETORESTORETOTHETHRONESIGNALRSTHANDOVERTOSCHMITTSTRIGGER,RESTORETOTHETHRONECIRCUITSAMPLETOOUTPUT,SCHMITTOFTRIGGERCONSTANTLYINEACHS5P2,MACHINEOFCYCLEINHAVINGONEMORE,THENJUSTGOTANDRESTOREDTOTHETHRONEANDOPERATEDTHENECESSARYSIGNALINSIDLYRESTORETOTHETHRONERESISTANCEOFCIRCUITGENERALLY,ELECTRICCAPACITYPARAMETERSUITABLEFOR6BRILLIANTTOSHAKE,CANISITRESTORETOTHETHRONESIGNALHIGHLEVELDURATIONGREATERTHAN2MACHINECYCLESTOGUARANTEEBEINGRESTOREDTOTHETHRONEINTHECIRCUITISSIMPLE,ITSFUNCTIONISVERYIMPORTANTPIECESOFONECHIPCOMPUTERSYSTEMCOULDNORMALRUNNING,SHOULDFIRSTCHECKITCANRESTORETOTHETHRONENOTSUCCEEDINGCHECKINGANDCANPOPONESHEADANDMONITORTHEPINWITHTHEOSCILLOGRAPHTENTATIVELY,PUSHANDISRESTOREDTOTHETHRONETHEKEY,THEWAVEFORMTHATOBSERVESANDHASENOUGHRANGEISEXPORTEDINSTANTANEOUS,CANALSOTHROUGHISITRESTORETOTHETHRONECIRCUITGROUPHOLDINGVALUECARRYONTHEEXPERIMENTTOCHANGE中文译文51系列单片机的功能和结构51系列单片机是INTEL公司设计的单片机产品。这家公司于1976年推出8位MCS48系列之后又在1980年推出了MCS51系列单片机。它属于这一类型很多行一个芯片的电脑芯片都如8051、8031、8751、80C51BH,80C31BH等,其基本组成、性能和基本教学制度,都是一样的8051通常是51系列的代表。每个单片机系统是由以下几个方面构成118微处理器CPU2片中内数据存储器RAM128B/256B中如果结果不在操作过程中,结果也要显示出来3存储器存储程序/可擦写可编程只读存储器4KB/8KB,用于保存程序和数据,初步形成片但并不存储器/可擦写可编程只读存储器在一些人的电脑芯片,如8031、8032、80C等(4四个8路运行的I/O口,P0,P1,P2,P3,每个口既可用作输入也可用作出口5两个定时/计数器,每个计时器/计数器可设立不同计数方式,用来计数外部事件,可以设置定时方式也可以和根据计算结果或定时控制实现控制计算6五个中断控制系统7一个全双工串行UART异步接收世界/发送UART,它是实现一个计算机芯片和一个计算机芯片之间通讯的一种串口8振荡器和时钟产生电路,需要考虑石英晶体微调能力,允许震荡平率位12MHZ,上述每个部分都是通过片内数据总线连接。其中CPU是计算机芯片的核心,他是计算机的指挥中心,由算数单元和控制单元组成算术单元可进行8位算术运算和逻辑运算,ALU单元是一种运算器,18个存储设备,暂存设备进行存储协调,PSW积累了两个输入端等检查时作为一个操作由人来操纵存储,另有一个操纵的结果回环协调。此外,协调往往是作为对8051的数据传输运转站考虑。作为一般的微处理器,他是最繁忙的。振荡器和定时器是由2个8位计数器组成,总位数为16位。这是一个字节的地址,其实是程序计数器,将在个人电脑内部有运行,从而改变程序的运行顺序。在8051的电路中,只需增加外部石英晶体和频率微调电容,这就保证计算机各部件的工作就像管弦乐队和谐工作。在8051中有ROM程序存储器,只能读取和RAM数据存储器,可读可写,他们有各自独立的内存地址空间,也有相同的处理方式。8051和8751的程序存储器的存储容量为4KB,地址从0000H开始,在使用过程中其中数据不变。8051,8751,8031数据存储器的内存为128B,默认地址是00FH,用于保存中间数据和缓存。在这128B的内存中,有32BYTESES,被称作工作寄存器,和常用的微处理器不同的是,8051的RAM是按功能来划分模块的。MCS51系列单片机和和一般电脑的处理方式不同。一般电脑会自动分配地址空间,ROM和RAM的计算机可以安排在不同的空间内,地址范围会根据ROM和RAM的位置分配不同的地址空间。在访问的内存,不管是ROM和RAM,只有一个地址对应一个内存单元,都要按这个顺序访问。这种内存结构是所谓的普林斯顿结构。8051的存储结构按物理结构划分可分为程序存储空间和数据存储空间,共有四个内存空间,按结构位置的不同分为内部程序存储空间,外部程序存储空间,内部数据存储空间,外部数据存储空间。但从用户的使用角
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