单片机毕业参考英文文献及翻译

STRUCTUREANDFUNCTIONOFTHEMCS51SERIESTHEMONOLITHICINTEGRATEDCIRCUITSAIDTHATTHEMONOLITHICMICROCONTROLLER,ITISNOTCOMPLETESSOMELOGICALFUNCTIONTHECHIP,BUTINTEGRATESACOMPUTERSYSTEMTOACHIPONSUMMARYSPEAKINGACHIPHASBECOMEACOMPUTERITSVOLUMEISSMALL,THEQUALITYISLIGHT,THEPRICECHEAP,FORTHESTUDY,THEAPPLICATIONANDTHEDEVELOPMENTHASPROVIDEDTHECONVENIENTCONDITIONATTHESAMETIME,THESTUDYUSEMONOLITHICINTEGRATEDCIRCUITISUNDERSTANDSTHECOMPUTERPRINCIPLEANDTHESTRUCTUREBESTCHOICETHEMONOLITHICINTEGRATEDCIRCUITINTERIORALSOUSESWITHTHECOMPUTERFUNCTIONSIMILARMODULE,FORINSTANCECPU,MEMORY,PARALLELMAINLINE,BUTALSOHASWITHTHEHARDDISKBEHAVEIDENTICALLYTHEMEMORYCOMPONENT,WHATISDIFFERENTISITSTHESEPARTPERFORMANCEISOPPOSITEOURHOMEUSECOMPUTERWEAKMANY,BUTTHEPRICEISALSOLOW,GENERALLYDOESNOTSURPASS10YUANTHENMADESOMECONTROLELECTRICAPPLIANCEONEKINDWITHITISNOTTHEVERYCOMPLEXWORKFOOTWEUSENOWTHECOMPLETELYAUTOMATICDRUMWASHER,THEPLATOONPETTICOATPIPE,VCDANDSOONINSIDETHEELECTRICALAPPLIANCESMAYSEEITSFORMITISMAINLYTAKESTHECONTROLSECTIONTHECOREPARTITISONEKINDOFONLINELIKEREALTIMCONTROLCOMPUTER,ONLINELIKEISTHESCENECONTROL,NEEDSTOHAVETHESTRONGANTIJAMMINGABILITY,THELOWCOST,THISISALSOANDTHEOFFLINETYPECOMPUTERFORINSTANCEHOMEUSEPCMAINDIFFERENCETHEMONOLITHICINTEGRATEDCIRCUITISDEPENDINGONTHEPROCEDURE,ANDMAYREVISEREALIZESTHEDIFFERENTFUNCTIONTHROUGHTHEDIFFERENTPROCEDURE,PARTICULARLYSPECIALUNIQUESOMEFUNCTIONS,THISISOTHERCOMPONENTNEEDSTOTAKETHEVERYBIGEFFORTTOBEABLETOACHIEVE,SOMEARETHEFLOWEREDBIGSTRENGTHISALSOVERYDIFFICULTTOACHIEVEONEISNOTTHEVERYCOMPLEXFUNCTION,IFDEVELOPSINTHE50SWITHTHEUS74SERIES,ORTHE60SSCD4000SERIESTHESEPUREHARDWAREDODECIDES,THEELECTRICCIRCUITCERTAINLYAREABIGPCBBOARDBUTIF,IFSUCCEEDEDINTHE70SWITHTHEUSPUTSINTHEMARKETTHESERIESMONOLITHICINTEGRATEDCIRCUIT,THERESULTWILLHAVETHEHUGEDIFFERENCEBECAUSEONLYTHEMONOLITHICINTEGRATEDCIRCUITCOMPILESTHROUGHYOUTHEPROCEDUREMAYREALIZETHEHIGHINTELLIGENCE,HIGHEFFICIENCY,ASWELLASREDUNDANTRELIABILITYSTRUCTUREANDFUNCTIONOFTHEMCS51SERIESONECHIPCOMPUTERMCS51ISANAMEOFAPIECEOFONECHIPCOMPUTERSERIESWHICHINTELCOMPANYPRODUCESTHISCOMPANYINTRODUCED8TOPGRADEONECHIPCOMPUTERSOFMCS51SERIESIN1980AFTERINTRODUCING8ONECHIPCOMPUTERSOFMCS48SERIESIN1976ITBELONGTOALOTOFKINDSTHISLINEOFONECHIPCOMPUTERTHECHIPSHAVE,SUCHAS8051,8031,8751,80C51BH,80C31BH,ETC,THEIRBASICCOMPOSITION,BASICPERFORMANCEANDINSTRUCTIONSYSTEMAREALLTHESAME8051DAILYREPRESENTATIVES51SERIALONECHIPCOMPUTERSANONECHIPCOMPUTERSYSTEMISMADEUPOFSEVERALFOLLOWINGPARTS1ONEMICROPROCESSOROF8CPU2ATSLICEDATAMEMORYRAM128B/256B,ITUSENOTDEPOSITTINGNOTCANREADING/DATATHATWRITE,SUCHASRESULTNOTMIDDLEOFOPERATION,FINALRESULTANDDATAWANTEDTOSHOW,ETC3PROCEDUREMEMORYROM/EPROM4KB/8KB,ISUSEDTOPRESERVETHEPROCEDURE,SOMEINITIALDATAANDFORMINSLICEBUTDOESNOTTAKEROM/EPROMWITHINSOMEONECHIPCOMPUTERS,SUCHAS8031,8032,80C,ETC4FOUR8RUNSIDEBYSIDEI/OINTERFACEP0FOURP3,EACHMOUTHCANUSEASINTRODUCTION,MAYUSEASEXPORTINGTOO5TWOTIMER/COUNTER,EACHTIMER/COUNTERMAYSETUPANDCOUNTINTHEWAY,USEDTOCOUNTTOTHEEXTERNALINCIDENT,CANSETUPINTOATIMINGWAYTOO,ANDCANACCORDINGTOCOUNTORRESULTOFTIMINGREALIZETHECONTROLOFTHECOMPUTER6FIVECUTOFFCUTTINGOFFTHECONTROLSYSTEMOFTHESOURCE7ONEALLDUPLEXINGSERIALI/OMOUTHOFUARTUNIVERSALASYNCHRONOUSRECEIVER/TRANSMITTERUART,ISITREALIZEONECHIPCOMPUTERORONECHIPCOMPUTERANDSERIALCOMMUNICATIONOFCOMPUTERTOUSEFOR8STRETCHOSCILLATORANDCLOCKPRODUCECIRCUIT,QUARTZCRYSTALFINELYTUNEELECTRICCAPACITYNEEDOUTERALLOWOSCILLATIONFREQUENCYAS12MEGAHERTASNOWATMOSTEVERYTHEABOVEMENTIONEDPARTWASJOINEDTHROUGHTHEINSIDEDATABUSAMONGTHEM,CPUISACOREOFTHEONECHIPCOMPUTER,ITISTHECONTROLOFTHECOMPUTERANDCOMMANDCENTRE,MADEUPOFSUCHPARTSASARITHMETICUNITANDCONTROLLER,ETCTHEARITHMETICUNITCANCARRYON8PERSONSOFARITHMETICOPERATIONANDUNITALUOFLOGICOPERATIONWHILEINCLUDINGONE,THE1STORINGDEVICETEMPORARILIESOF8,STORINGDEVICE2TEMPORARILY,8SACCUMULATIONDEVICEACC,REGISTERBANDPROCEDURESTATEREGISTERPSW,ETCPERSONWHOACCUMULATEACCCOUNTBY2INPUTENDSENTEREDOFCHECKINGETCTEMPORARILYASONEOPERATIONOFTEN,COMEFROMPERSONWHOSTORE1OPERATIONISITISITMAKEOPERATIONTOGOONTOCOUNTTEMPORARILY,OPERATIONRESULTANDLOOPBACKACCWITHANOTHERONEINADDITION,ACCISOFTENREGARDEDASTHETRANSFERSTATIONOFDATATRANSMISSIONON8051INSIDETHESAMEASGENERALMICROPROCESSOR,ITISTHEBUSIESTREGISTERHELPREMEMBERINGTHATAGREEINGWITHAEXPRESSESINTHEORDERTHECONTROLLERINCLUDESTHEPROCEDURECOUNTER,THEORDERISDEPOSITTED,THEORDERDECIPHER,THEOSCILLATORANDTIMINGCIRCUIT,ETCTHEPROCEDURECOUNTERISMADEUPOFCOUNTEROF8FORTWO,AMOUNTSTO16ITISABYTEADDRESSCOUNTEROFTHEPROCEDUREINFACT,THECONTENTISTHENEXTIATHATWILLCARRIEDOUTINPCTHECONTENTWHICHCHANGESITCANCHANGETHEDIRECTIONTHATTHEPROCEDURECARRIESOUTSHAKETHECIRCUITIN8051ONECHIPCOMPUTERS,ONLYNEEDOUTERQUARTZCRYSTALANDFREQUENCYTOFINELYTUNETHEELECTRICCAPACITY,ITSFREQUENCYRANGEISITS12MHZOF12MHZTHISPULSESIGNAL,AS8051BASICBEATSOFWORKING,NAMELYTHEMINIMUMUNITOFTIME8051ISTHESAMEASOTHERCOMPUTERS,THEWORKINHARMONYUNDERTHECONTROLOFTHEBASICBEAT,JUSTLIKEANORCHESTRAACCORDINGTOTHEBEATPLAYTHATISCOMMANDEDTHEREAREROMPROCEDUREMEMORY,CANONLYREADANDRAMIN8051SLICESDATAMEMORY,CANISITCANWRITETWOTOREAD,THEYHAVEEACHINDEPENDENTMEMORYADDRESSSPACE,DISPOSEWAYTOBETHESAMEWITHGENERALMEMORYOFCOMPUTERPROCEDURE8051MEMORYAND8751SLICEPROCEDUREMEMORYCAPACITY4KB,ADDRESSBEGINFROM0000H,USEDFORPRESERVINGTHEPROCEDUREANDFORMCONSTANTDATA805187518031OFMEMORYDATAMEMORY128B,ADDRESSFALSE00FH,USEFORMIDDLERESULTTODEPOSITOPERATION,THEDATAARESTOREDTEMPORARILYANDTHEDATAAREBUFFEREDETCINRAMOFTHIS128B,THEREISUNITOF32BYTESESTHATCANBEAPPOINTEDASTHEJOBREGISTER,THISANDGENERALMICROPROCESSORISDIFFERENT,8051SLICERAMANDJOBREGISTERRANKONEFORMATIONTHESAMETOARRANGETHELOCATIONITISNOTVERYTHESAMETHATTHEMEMORYOFMCS51SERIESONECHIPCOMPUTERANDGENERALCOMPUTERDISPOSESTHEWAYINADDITIONGENERALCOMPUTERFORFIRSTADDRESSSPACE,ROMANDRAMCANARRANGEINDIFFERENTSPACEWITHINTHERANGEOFTHISADDRESSATWILL,NAMELYTHEADDRESSESOFROMANDRAM,WITHDISTRIBUTINGDIFFERENTADDRESSSPACEINAFORMATIONWHILEVISITINGTHEMEMORY,CORRESPONDINGANDONLYANADDRESSMEMORYUNIT,CANROM,ITCANBERAMTOO,ANDBYVISITINGTHEORDERSIMILARLYTHISKINDOFMEMORYSTRUCTUREISCALLEDTHESTRUCTUREOFPRINCETON8051MEMORIESAREDIVIDEDINTOPROCEDUREMEMORYSPACEANDDATAMEMORYSPACEONTHEPHYSICSSTRUCTURE,THEREAREFOURMEMORYSPACESINALLTHEPROCEDURESTORESINONEANDDATAMEMORYSPACEOUTSIDEDATAMEMORYANDONEINPROCEDUREMEMORYSPACEANDONEOUTSIDEONE,THESTRUCTUREFORMSOFTHISKINDOFPROCEDUREDEVICEANDDATAMEMORYSEPARATEDFORMDATAMEMORY,CALLEDHARVARDSTRUCTUREBUTUSETHEANGLEFROMUSERS,8051MEMORYADDRESSSPACEISDIVIDEDINTOTHREEKINDS1INTHESLICE,ARRANGEBLOCKSOF0FFFH,0000HOFLOCATION,INUNISONOUTSIDETHESLICEUSE16ADDRESSES2THEDATAMEMORYADDRESSSPACEOUTSIDEONEOF64KB,THEADDRESSISARRANGEDFROM0000H64KBFFFFHWITH16ADDRESSESTOOTOTHELOCATION3DATAMEMORYADDRESSSPACEOF256BUSE8ADDRESSESTHREEABOVEMENTIONEDMEMORYSPACEADDRESSESOVERLAP,FORDISTINGUISHINGANDDESIGNINGTHEORDERSYMBOLOFDIFFERENTDATATRANSMISSIONINTHEINSTRUCTIONSYSTEMOF8051CPUVISITSLICE,ROMORDERSPENDMOVC,VISITBLOCKRAMORDERUSESMOVXOUTSIDETHESLICE,RAMORDERUSESMOVTOVISITINSLICE8051ONECHIPCOMPUTERHAVEFOUR8WALKABREASTI/OPORT,CALLP0,P1,P2ANDP3EACHPORTIS8ACCURATETWOWAYMOUTHS,ACCOUNTSFOR32PINSALTOGETHEREVERYONEI/OLINECANBEUSEDASINTRODUCTIONANDEXPORTEDINDEPENDENTLYEACHPORTINCLUDESALATCHNAMELYSPECIALFUNCTIONREGISTER,ONEEXPORTSTHEDRIVERANDAINTRODUCTIONBUFFERMAKEDATACANLATCHWHENOUTPUTTING,DATACANBUFFERWHENMAKINGINTRODUCTION,BUTFOURFUNCTIONOFPASSWAYTHESESELFSAMEEXPANDAMONGTHESYSTEMOFMEMORYOUTSIDENOTHAVINGSLICE,FOURPORTTHESEMAYSERVEASACCURATETWOWAYMOUTHOFI/OINCOMMONUSEEXPANDAMONGTHESYSTEMOFMEMORYOUTSIDEHAVINGSLICE,P2MOUTHSEEHIGH8ADDRESSOFFP0MOUTHISATWOWAYBUS,SENDTHEINTRODUCTIONOF8LOWADDRESSESANDDATA/EXPORTINTIMESHARINGTHECIRCUITOF8051ONECHIPCOMPUTERSANDFOURI/OPORTSISVERYINGENIOUSINDESIGNFAMILIARWITHI/OPORTLOGICALCIRCUIT,NOTONLYHELPTOUSEPORTSCORRECTLYANDRATIONALLY,ANDWILLINSPIRETODESIGNINGTHEPERIPHERALLOGICALCIRCUITOFONECHIPCOMPUTERTOSOMEEXTENTLOADABILITYANDINTERFACEOFPORTHAVECERTAINREQUIREMENT,BECAUSEOUTPUTGRADE,P0OFMOUTHANDP1ENDOUTPUT,P3OFMOUTHGRADEDIFFERENTATSTRUCTURE,SO,THELOADABILITYANDINTERFACEOFITSDOORDEMANDTOHAVENOTHINGINCOMMONWITHEACHOTHERP0MOUTHISDIFFERENTFROMOTHERMOUTHS,ITSOUTPUTGRADEDRAWSTHERESISTANCESUPREMLYWHENUSINGITASTHEMOUTHINCOMMONUSETOUSE,OUTPUTGRADEISITLEAKCIRCUITTOTURNON,ISITISITURGENMOSDRAWTHERESISTANCEONTAKINGTOBEOUTERWITHITWHILEINPUTTINGTOGOOUTTOFAILWHENBEINGUSEDASINTRODUCTION,SHOULDWRITE“1“TOALATCHFIRSTEVERYONEWITHP0MOUTHCANDRIVE8MODELLSTTLLOADTOEXPORTP1MOUTHISANACCURATETWOWAYMOUTHTOO,USEDASI/OINCOMMONUSEDIFFERENTFROMP0MOUTHOUTPUTOFCIRCUITITS,DRAWLOADRESISTANCELINKWITHPOWERONINSIDEHAVEINFACT,THERESISTANCEISTHATTWOEFFECTSAREINCHARGEOFFETANDTOGETHERONEFETISINCHARGEOFLOAD,ITSRESISTANCEISREGULARANOTHERONECANISITLEADTOWORKWITHCLOSEATTWOSTATE,MAKEITSPRESIDENTRESISTANCEVALUECHANGEAPPROXIMATE0ORGROUPVALUEHEAVYTWOSITUATIONVERYWHENITIS0THATTHERESISTANCEISAPPROXIMATE,CANDRAWTHEPINTOTHEHIGHLEVELFASTWHENRESISTANCEVALUEISVERYLARGE,P1MOUTH,INORDERTOHINDERTHEINTRODUCTIONSTATEHIGHOUTPUTASP1MOUTHHIGHELECTRICITYATORDINARYTIMES,CANISITDRAWELECTRICCURRENTLOADTOOFFEROUTWARDS,DRAWTHERESISTANCEONNEEDNTANSWERANDTHENNINGHEREWHENTHEPORTISUSEDASINTRODUCTION,MUSTWRITEINTO1TOTHECORRESPONDINGLATCHFIRSTTOO,MAKEFETENDRELATIVELYABOUT20,000OHMSBECAUSEOFTHELOADRESISTANCEINSCENEANDBECAUSE40,000OHMS,WILLNOTEXERTANINFLUENCEONTHEDATATHATAREINPUTTHESTRUCTUREOFP2SOMEMOUTHISSIMILARTOP0MOUTH,THEREAREMUXSWITCHESISITSIMILARTOMOUTHPARTLYTOURGE,BUTMOUTHLARGEACONVERSIONCONTROLSSOMETHANP1P3MOUTHONEMULTIFUNCTIONALPORT,MOUTHGETTINGMANYTHANP1ITHAVE“AND“3DOORAND4BUFFER“TWOPARTTHESE,MAKEHERBESIDESACCURATETWOWAYFUNCTIONWITHP1MOUTHJUST,CANALSOUSETHESECONDFUNCTIONOFEVERYPIN,“AND“DOOR3FUNCTIONONESWITCHINFACT,ITDETERMINESTOBETOOUTPUTDATAOFLATCHTOOUTPUTSECONDSIGNALOFFUNCTIONACTASWAT1OCLOCK,OUTPUTQENDSIGNALACTASQAT1OCLOCK,CANOUTPUTWLINESIGNALATTHETIMEOFPROGRAMMING,ITISTHATTHEFIRSTFUNCTIONISSTILLTHESECONDFUNCTIONBUTNEEDNTHAVESOFTWARETHATSETUPP3MOUTHINADVANCEITHARDWARENOTINSIDEISTHEAUTOMATICTOHAVETWOFUNCTIONOUTPUTTEDWHENCPUCARRIESONSFRANDSEEKSTHELOCATIONTHELOCATIONORTHEBYTETOVISITTOP3MOUTH/ATNOTLASTINGLINING,THEREAREINSIDEHARDWARELATCHQS1THEOPERATIONPRINCIPLEOFP3MOUTHISSIMILARTOP1MOUTHOUTPUTGRADE,P3OFMOUTH,P1OFP1,CONNECTWITHINSIDEHAVELOADRESISTANCEOFDRAWING,EVERYONEOFTHEYCANDRIVE4MODELLSTTLLOADTOOUTPUTASWHILEINPUTTINGTHEMOUTH,ANYTTLORNMOSCIRCUITCANDRIVEP1OF8051ONECHIPCOMPUTERSASP3MOUTHINANORMALWAYBECAUSEDRAWRESISTANCEONOUTPUTGRADEOFTHEMHAVE,CANOPENAWAYCOLLECTORTOOORDRAINSOURCERESISTANCEISITURGETOOPENAWAY,DONOTNEEDTOHAVETHERESISTANCEOFDRAWINGOUTERLYMOUTHSAREALLACCURATETWOWAYMOUTHSTOOWHENTHECONDUCTISINPUT,MUSTWRITETHECORRESPONDINGPORTLATCHWITH1FIRSTASTO80C51ONECHIPCOMPUTER,PORTCANONLYOFFERMILLIAMPEREOFOUTPUTELECTRICCURRENTS,ISITOUTPUTMOUTHGOWHENURGINGONEORDINARYBASINGOFTRANSISTORTOREGARDAS,SHOULDCONTACTARESISTANCEAMONGTHEPORTANDTRANSISTORBASE,INORDERTOTHEELECTRICITYWHILERESTRAININGTHEHIGHLEVELFROMEXPORTINGP1P3BEINGRESTOREDTOTHETHRONEISTHEOPERATIONOFINITIALIZINGOFANONECHIPCOMPUTERITSMAINFUNCTIONISTOTURNPCINTO0000HINITIALLY,MAKETHEONECHIPCOMPUTERBEGINTOHOLDTHECONDUCTPROCEDUREFROMUNIT0000HEXCEPTTHATTHEONESTHATENTERTHESYSTEMAREINITIALIZEDNORMALLY,ASBECAUSEPROCEDUREOPERATEITMAKEMISTAKESOROPERATETHEREARENTMISTAKE,INORDERTOEXTRICATEONESELFFROMAPREDICAMENT,NEEDTOBEPRESSEDANDRESTOREDTOTHETHRONETHEKEYRESTARTINGTOOITISANINPUTENDWHICHISRESTOREDTOTHETHRONETHESIGNALIN8051CHINARSTPINRESTORETOTHETHRONESIGNALHIGHLEVELEFFECTIVE,SHOULDSUSTAIN24SHAKECYCLENAMELY2MACHINECYCLESTHEABOVEITSEFFECTIVETIMESIF6OFFREQUENCYOFUTILIZATIONBRILLIANTTOSHAKE,RESTORETOTHETHRONESIGNALDURATIONSHOULDEXCEED4DELICATETOFINISHRESTORINGTOTHETHRONEANDOPERATINGPRODUCETHELOGICPICTUREOFCIRCUITWHICHISRESTOREDTOTHETHRONETHESIGNALRESTORETOTHETHRONETHECIRCUITANDINCLUDETWOPARTSOUTSIDEINTHECHIPENTIRELYOUTSIDETHATCIRCUITPRODUCETORESTORETOTHETHRONESIGNALRSTHANDOVERTOSCHMITTSTRIGGER,RESTORETOTHETHRONECIRCUITSAMPLETOOUTPUT,SCHMITTOFTRIGGERCONSTANTLYINEACHS5P2,MACHINEOFCYCLEINHAVINGONEMORE,THENJUSTGOTANDRESTOREDTOTHETHRONEANDOPERATEDTHENECESSARYSIGNALINSIDLYRESTORETOTHETHRONERESISTANCEOFCIRCUITGENERALLY,ELECTRICCAPACITYPARAMETERSUITABLEFOR6BRILLIANTTOSHAKE,CANISITRESTORETOTHETHRONESIGNALHIGHLEVELDURATIONGREATERTHAN2MACHINECYCLESTOGUARANTEEBEINGRESTOREDTOTHETHRONEINTHECIRCUITISSIMPLE,ITSFUNCTIONISVERYIMPORTANTPIECESOFONECHIPCOMPUTERSYSTEMCOULDNORMALRUNNING,SHOULDFIRSTCHECKITCANRESTORETOTHETHRONENOTSUCCEEDINGCHECKINGANDCANPOPONESHEADANDMONITORTHEPINWITHTHEOSCILLOGRAPHTENTATIVELY,PUSHANDISRESTOREDTOTHETHRONETHEKEY,THEWAVEFORMTHATOBSERVESANDHASENOUGHRANGEISEXPORTEDINSTANTANEOUS,CANALSOTHROUGHISITRESTORETOTHETHRONECIRCUITGROUPHOLDINGVALUECARRYONTHEEXPERIMENTTOCHANGEMCS51系列单片机的功能和结构单片机又称单片微控制器,它不是完成某一个逻辑功能的芯片,而是把一个计算机系统集成到一个芯片上。概括的讲一块芯片就成了一台计算机。它的体积小、质量轻、价格便宜、为学习、应用和开发提供了便利条件。同时，学习使用单片机是了解计算机原理与结构的最佳选择。单片机内部也用和电脑功能类似的模块，比如CPU，内存，并行总线，还有和硬盘作用相同的存储器件，不同的是它的这些部件性能都相对我们的家用电脑弱很多，不过价钱也是低的，一般不超过10元即可用它来做一些控制电器一类不是很复杂的工作足矣了。我们现在用的全自动滚筒洗衣机、排烟罩、VCD等等的家电里面都可以看到它的身影它主要是作为控制部分的核心部件。它是一种在线式实时控制计算机，在线式就是现场控制，需要的是有较强的抗干扰能力，较低的成本，这也是和离线式计算机的（比如家用PC）的主要区别。单片机是靠程序的，并且可以修改。通过不同的程序实现不同的功能，尤其是特殊的独特的一些功能，这是别的器件需要费很大力气才能做到的，有些则是花大力气也很难做到的。一个不是很复杂的功能要是用美国50年代开发的74系列，或者60年代的CD4000系列这些纯硬件来搞定的话，电路一定是一块大PCB板但是如果要是用美国70年代成功投放市场的系列单片机，结果就会有天壤之别只因为单片机的通过你编写的程序可以实现高智能，高效率，以及高可靠性MCS51系列单片机的结构和功能。MCS51单片机是英特尔公司生产的一个单芯片电脑系列,1980年后，这家公司生产的8位MCS51系列单片机于1976年引入8位MCS48单片机。它属于很多这一类型的单片机，例如8051、8031、8751、80C51BH,80C31BH等,它们的基本组成结构、基本性能和指令系统都是一样的805151系列单片机的代表之一。一个单片机系统是由以下几个方面组成1一个8位处理器CPU。2在一个数据存储器RAM128B/256B中,它通常不存放不能读写的数据，像不操作的结果,最终结果和要显示的数据等。3程序存储器ROM/EPROM4KB/8KB,用于保存初始程序和数据,形成片区。但一些单片机中并不存在程序存储器ROM/EROM,如8031、8032、80C等。（4）四个8位双向接口P0到P3,每个口可以用作引导口,也可以用作输出口。5两个定时器/计数器,每个定时器/计数器可设置和计数用来计算外部事件,也可设置定时的方式，并可以根据计算或计时结果来实现计算机得控制。6五个中断源控制系统7一个全双工一部串行口I/O属于UART（通用异步接收器/发送器（UART）,它是用于实现单片机或单片机和计算机的串行通信。8内振荡器和时钟电路，石英晶体和需要的外部电容晶振频率现在最多允许12兆赫的频率振荡。上述每个部分都加入了通过内部的数据总线。其中,CPU是一个单片机的核心,它是单片机的控制和指挥中心，由运算器和控制器等部分组成。运算器可进行8位算术运算同时还包含一个逻辑运算单元ALU，8位由暂存器1，暂存器2，累加器ACC，寄存器B，以及程序状态字寄存器PSW等组成。当数据从暂存器2计数检查进入累加器ACC，暂时作为一个通常由暂存器1来操作,它使运算的暂时计算结果回送到另一个累加器ACC。此外,累加器ACC往往被视为8051内数据传输的中转站。和普通的微处理器一样，它是最繁忙的寄存器。帮助记取一个同意的命令。该控制器包括程序计数器,，顺序存放，解密的顺序，振荡器电路和定时电路等。该程序计数器是由两对8位计数器组成，达到16位。实际上这是一个字节地址计数器的程序,内容是展开度个人电脑的一个执行机构。改变它的内从从而可以改变该程序执行的方向。在8051单片机的振荡电路中，仅采用石英晶体外和微调电容,其晶振频率范围为12MZH到12MZH。这一脉冲信号作为8051工作时，最小单位时间的基本频率。8051同其他单片机一样,在恰当的基本频率下工作,就像一个乐团,跟随着指挥演奏。8051单片机内存在只读存储器ROM程序存储器,只能读,和随机存储器RAM存储数据,是可以写出二种存储器,它们每个有各自独立的内存地址空间,处理方式与电脑的内存是一样的。8051和8751单片机的程序存储器为4KB,地址从0000H开始,用于保存程序的方式不变。8051和8751数据存储器数据为128B,虚假地址00FH,通常用于中层结果存入操作使用,暂时的数据存储和数据缓冲等。在数据存储器RAM的128B中，每一个单元有32字节可为寄存器工作，和通用的微处理器不同的是，8051单片机数据存储器RAM安排的任务记录于同一级的一个编队。MCS51系列单片机和一般的计算机芯片不大相同的是删除了一般电脑的方式处置。一般电脑的第一个地址空间在这个地址范围内程序存储器ROM和数据存储器RAM可以安排在不同的空间内，即ROM程序存储器的地址和数据存储器RAM地址分布在不同的地址空间形成。同时来访的内存，只有一个地址对应的内存单元，可以是程序存储器ROM也可以是数据存储器RAM，并以同样的访问。这种内存结构是所谓的普林斯顿结构。8051按内存物理结构分为程序存储空间和数据存储空间，有四个在所有的存储空间我们的程序和数据储存在一个外部数据存储器的存储空间个程序存储空间外一个接一个，这种程序和数据存储设备的数据存储形式是一种分离的结构形式，称为哈佛结构。但从使用用户的角度8051存储器地址空间被分为三种（1）在单片机内部地址位置从0000H到0FFFH，与片外的一致（使用十六地址）。（2）外部数据存储器地址空间64KB之一,被安排从地址1000H64KB到FFFFH（含16个地址）,外置也一样。（3）256B的数据存储器地址空间（使用8个地址）。上述三个存储空间地址重叠，用于区分和设计不同的数据在8051指令系统的传输秩序的象征CPU访问单片机，以便用程序存储器ROM执行MOVC问命令，访问RAM以便使用片外的MOVX，内存呢以便使用MOVX访问单片机。8051单片机有4个8位并行的I/O端口，分别叫P0、P1、P2和P3。每个端口都是8位准确双向口,共占了32针。每一个I/O口线可作为独立的引进和输出口。每个端口包含一个锁存器（即特殊功能寄存器）一个输入缓冲器。使数据能锁存输出，数据缓冲是可以引入，不过这四个功能的通道各自相同。在无片外扩展存储器的系统中，这四个端口的每一位都可