《电子技术数字基础 Digital Fundamentals》双语课件PPT-第08章 Counters (1)

1、1,chapter 8 counters (and the sequential logic),2,contents,introduction analysis of the sequential logic counters design of sequential logics,3,8-0 introduction,the digital electronic logic is classified as the combinational logic and the sequential logic. (数字电路分为：组合逻辑电路及时序逻辑电路) the sequential logic

2、 includes the combinational logic section and the memory section.,4,8-0 introduction,the logic diagram for the general sequential logic,com-bina-tional logic,memory,x = (x1 ,x2 ,xi,),y = (y1 ,y2 ,yj,),q = (q1 ,q2 ,ql,),z = (z1 ,z2 ,zk,),y = fx,q,z = gx,q,qn+1 = hz,qn,output exp.,state exp.,excitatio

3、n exp.,输出方程,驱动方程,状态方程,5,8-0 introduction,the sequential logic is classified as the asynchronous one and synchronous one (异步时序电路和同步时序电路）. the analysis and design of the sequential logic is discussed in this chapter. and the counter is the most useful device.,6,8-2 synchronous counter operation (同步计数器

4、）,4. assume the present state, and analyze the next state, and draw its state diagram (状态转换图) /state sequence table(状态转换表)or its timing diagram （时序图）.,5. determine the logic function of the logic diagram.,10,8-2-1 analysis of the sequential logic example1,ex.1 determine the logic function.,synchrono

5、us sequential logic,write down the clock and excitation expressions for each ff.,toggle at the positive edge.,t ff j=k=1,11,8-2-1 analysis of the sequential logic example1,4. assume the present sate, and analyze the next state, and draw its state diagram / state sequence table or its timing diagram.

6、,12,8-2-1 1 analysis of the sequential logic state sequence table (状态转换表),state sequence table,13,8-2-1 analysis of the sequential logic state diagram (状态转换图),00,01,10,11,state sequence table,state diagram,q1q0,14,8-2-1 analysis of the sequential logic timing diagram (时序图),timing diagram,15,8-2-2 a

7、2-bit synchronous binary counter,a 2-bit synchronous binary counter (2位同步二进制/4进制 加法计数器）,16,8-2-3 a 3-bit synchronous binary counter,ex.2 determine the logic function.,17,8-2-3 a 3-bit synchronous binary counter,18,8-2-3 a 3-bit synchronous binary counter,a 3-bit synchronous binary counter (3位同步二进制/8

8、进制 加法计数器）,19,8-2-4 a 4-bit synchronous decade counter,20,8-2-4 a 4-bit synchronous decade counter,21,8-2-4 a 4-bit synchronous decade counter,a 1-bit synchronous decade counter (同步十进制加法计数器）,22,8-1 asynchronous counter operation (异步计数器),asynchronous: refers to events that do not have a fixed time rel

9、ationship with each other and, generally, do not occur at the same time. asynchronous counter: counter in which the ff do not change states at exactly the same time because they do not have a common clock pulse.,23,8-1-1 analysis of asynchronous sequential logic,determine the logic function.,asynchr

10、onous sequential logic,24,8-1-1 analysis of asynchronous sequential logic,25,8-1-1 analysis of asynchronous sequential logic,26,8-1-1 analysis of asynchronous sequential logic,27,8-1-1 analysis of asynchronous sequential logic,28,8-1-1 analysis of asynchronous sequential logic,state sequence table,s

11、tate diagram,a asynchronous decade counter (异步十进制加法计数器）,29,8-1-2 some useful concepts,valid states (used states) (有效状态) states used by the diagram in normal operation. invalid states (unused states)(无效状态） states which arent used by the diagram in normal operation.,30,8-1-2 some useful concepts,valid

12、 states,invalid states,valid cycle,invalid cycle,31,8-1-2 some useful concepts,valid cycle (有效循环) cycle that includes the valid states. invalid cycle(无效循环） cycle that includes the invalid states.,32,8-1-2 some useful concepts,startup automatically (自启动功能) if a logic diagram doesnt have invalid cycle

13、(无效循环), it can startup automatically. (电路进入无效状态之后,在cp脉冲作用下,能自动返回有效循环,称电路能够自启动,否则为不能自启动） self-startup check (自启动检查) check if all the invalid states can enter the valid cycle automatically.,33,state diagram,startup automatically,self-startup check,34,8-3 counters 8-3-1 categories of counters,the count

14、er can be classified as the following categories:,35,8-3-1 categories of counters,modulus-2 counter (2进制）,modulus-10 counter (10进制）,modulus-60 counter (60进制）,modulus-m counter (m进制,任意进制）,36,8-2-5 synchronous binary counters,c=q0q1q2q3,negative edge- triggered,37,8-2-5 synchronous binary counters,the

15、 counter is also called the frequency divider (分频器).,c=q0q1q2q3,38,8-2-5 synchronous binary counters -74161 msi modulus-16 counter,counter, divider, modulus-16 (16进制),39,8-2-5 74161 msi modulus-16 counter,parallel data inputs (并行输入端）,data outputs /states,clock pulse active at the positive edge,ent,e

16、np: enable pins,40,8-2-5 74161 msi modulus-16 counter,41,8-2-5 74161 msi modulus-16 counter,preset input (load) (预置端）(同步预置) active-low, synchronously,clear input (清零端）(异步清零) active-low, asynchronously,42,8-2-5 74161 msi modulus-16 counter,at the terminal count of 15, rco=1.,ripple clock output (进位脉冲

17、),43,8-2-5 74161 msi modulus-16 counter,state diagram,timing diagram,44,8-2-5 74161/74163 msi modulus-16 counter,logic function table(功能表） for 74161/74163,45,8-2-5 74161/74163 msi modulus-16 counter,clear input (清零端） (异步清零) active-low, asynchronously,46,8-2-5 74161/74163 msi modulus-16 counter,prese

18、t input (load) (预置端）(同步预置) active-low, synchronously,47,8-2-5 74161/74163 msi modulus-16 counter,only when both of ep and et are active, is the counter enabled (in counter operation).,the outputs plus one at the positive-edge of cp,48,8-2-5 74161/74163 msi modulus-16 counter,only when both of ep and

19、 et are active, is the counter enabled (in counter operation).,49,8-2-5 74160 msi modulus-10 counter,74160 synchronous bcd decade counter (ctr div 10 modulus-10, 10 states),50,8-2-5 74160 msi modulus-10 counter,clear asynchronously 异步清零,the clear input is active-low.,51,8-2-5 74160 msi modulus-10 co

20、unter,a timing diagram showing the counter being preset to count 7 (0111).,preset synchronously 同步预置,when the preset input is nonactive, the parallel inputs have no use.,the outputs are preset to the corresponding data input only at the active edge of cp.,52,8-2-5 74160 msi modulus-10 counter,when t

21、he terminal count is 9 (tc=9), rco=1,53,8-2-5 74160 msi modulus-10 counter,if any of enp and ent is nonactive (low), the outputs are disabled, remain in present states,54,8-3 up/down synchronous counters(可逆/加减计数器),by the control of the up/down input, the counter, on one hand, can increase one by one

22、; on the other hand, can also decrease one by one. this kind of counter is called up/down (加减) one, bidirectional （可逆）counter, also.,55,8-3 up/down synchronous counters,a basic 3-bit up/down synchronous counter,56,8-3 up/down synchronous counters,up/down sequence for a 3-bit binary counter,state seq

23、uence table for a 3-bit binary counter,57,8-3 up/down synchronous counters,state diagram,q2q1q0,up sequence,down sequence,58,8-3 up/down synchronous counters,logic function table for msi 74191- a synchronous modulus-16 up/down counter,preset asynchronously 异步预置,59,8-3 up/down synchronous counters,lo

24、gic symbol for msi 74190- a synchronous modulus-10 up/down counter,60,8-3 up/down synchronous counters,timing example for a 74190,preset asynchronously 异步预置,61,8-4 design of sequential logics(时序电路设计),sequential logic design,ssi sequential logic design(小规模) - design sequential logic using flip-flops

25、用触发器设计时序电路,msi sequential logic design(中规模) - design modulus-m counter using msi modulus-n counter 用n进制中规模集成计数器设计任意m进制计数器,62,8-4-1 ssi sequential logic design- sequential logics design using ff,procedure: step 1: convert the given problem to a logic problem. assume the input, output and state variab

26、les. step 2: get its state diagram. step 3: get its state sequence table. step 4: according to the number of the states, draw a corresponding number-variable k-map.,63,8-4-1 sequential logics design using ff,step 5: get the state expressions using k-map. step 6: choose the needed flip-flop. step 7:

27、get the excitation expressions according to the state expressions and logic expression for the corresponding flip-flop. step 8: sketch the logic diagram.,64,8-4-1 sequential logics design using ffexample 1,ex.1: design a modulus-13 counter with cascaded output.,step 1: assume the input, output and s

28、tate variables.,output: c state variables: s0,s1s12,state diagram.,65,8-4-1 sequential logics design using ffexample 1,13 states: 4 flip-fops (13 =24),step 2: state sequence table.,66,8-4-1 sequential logics design using ffexample 1,step 3: next-state k-map.,present state: 0000,next state: 0001 outp

29、ut: 0,dont care conditions,67,8-4-1 sequential logics design using ffexample 1,step 4: get k-map for each state. (optional),68,8-4-1 sequential logics design using ffexample 1,step 5: get the state expressions.,69,8-4-1 sequential logics design using ffexample 1,step 5: get the output expression.,c=

30、q3q2,step 6: choose the flip-flop: j-k flip-flop.,70,8-4-1 sequential logics design using ffexample 1,step 7: get the excitation expression.,71,8-4-1 sequential logics design using ffexample 1,step 8: draw the logic diagram.,c=q3q2,72,8-4-1 sequential logics design using ffexample 1,step 9: self-sta

31、rtup check (自启动检查),it can startup automatically.,73,8-4-1 sequential logics design using ffexample 2,ex. 2: design a logic diagram that can check the series data. when there are three or more than three high inputs in series, the output is 1; otherwise , the output is 0. 设计一个串行数据检测器。当连续输入3个或3个以上1的时候

32、，输出为1；否则为0。,74,8-4-1 sequential logics design using ffexample 2,step 1: analyze the problem, assume the input/output variables, and get its state diagram/state sequence table.,assume: x: the input variable; y: the output variable; states: s0 the input is 0; s1 there is only one high input. s2 there

33、is two high inputs in series. s3 there is three or more than three high inputs in series.,75,8-4-1 sequential logics design using ffexample 2,step 2: state sequence table,equivalent states (等价状态),the input,76,8-4-1 sequential logics design using ffexample 2,step 3: k-map,00,01,10,3 states: 2 flip-fo

34、ps (3 =22),77,8-4-1 sequential logics design using ffexample 2,78,8-4-1 sequential logics design using ffexample 2,step 4: state expressions,step 5: output expression,y=x q1,79,8-4-1 sequential logics design using ffexample 2,step 6: choose the flip-flop: j-k flip-flop.,step 7: get the excitation ex

35、pressions.(驱动方程),80,8-4-1 sequential logics design using ffexample 2,step 8: construct the logic diagram.,y=x q1,81,8-4-1 sequential logics design using ffexample 2,step 9: check whether the diagram startup automatically.,it can startup automatically.,82,8-4-1 sequential logics design using ffexampl

36、e 2,implement the above logic function using d flip-flop.,y=x q1,83,8-4-1 sequential logics design using ffexample 2,y=x q1,84,8-4-2 sequential logics design using msi counters,analysis of sequential logics with msi counters,85,8-4-2 analysis of sequential logics with msi counters i using the preset

37、 input,determine the modulus (logic function) of the given logic diagram, and the logic function table of 74160 is shown as the following table.,86,modulus-7 counter 7进制计数器,stable state,valid cycle,87,8-4-2 analysis of sequential logics with msi counters ii using the clear input,88,momentary / astab

38、le state 瞬态/暂态,modulus-10 counter 10进制计数器,89,8-4-2 analysis of sequential logics with msi counters - ii using the clear input,modulus-10 counter 10进制计数器,y(q3): cascaded output 进位输出端,90,8-4-2 analysis of sequential logics with msi counters- ii using the clear input,0000,0001,0010,0011,0110,1000,0100,

39、0101,0111,1001,1010,y(q3): cascaded output,91,8-4-2 analysis of sequential logics with msi counters- ii using the clear input,improved logic diagram using the clear input,cascaded output,92,8-4-2 analysis of sequential logics with msi counters 8-5(iii) cascaded counters,counters can be connected in

40、cascade to achieve higher-modulus operation. cascading means that the last-stage output of one counter drives the input of the next counter.,93,8-5 cascaded counters,the final output q4 occurs once for every 32 input clock pulses.,94,8-5 cascaded counters,the overall modulus of the cascaded counters

41、 is 32, that is, they act as a divide-by-32 counter. (整个电路为32进制计数器). in general, the overall modulus of cascaded counters is equal to the product of the individual moduli. for instance, the overall modulus of the given circuit is 48=32.,95,8-5 cascaded counters,this is asynchronous counters in a cas

42、caded configuration.,96,8-5 cascaded counters addition: 74290 msi asynchronous counter,97,98,8-5addition: 74290 msi asynchronous counter,99,q3q2q1q0,8-5addition: 74290 msi asynchronous counter,100,8-5addition: 74290 msi asynchronous counter,101,8-5addition: 74290 msi asynchronous counter,q0q3q2q1,10

43、2,8-5addition: 74290 msi asynchronous counter,103,logic function table for 74290 (2-5-10 counter),asynchronous clear and set-9 inputs,104,9-5 cascaded counters,when operation synchronous counters in a cascaded configuration, it is necessary to use the count enable and the terminal count functions to

44、 achieve higher-modulus operation.,modulus-100 conter,105,8-5 cascaded counters,106,8-4-2 analysis of sequential logics with msi counters iv cascaded counter analysis,modulus-7,modulus-6,modulus-42 (76),107,8-4-3 sequential logics design using msi counter,design a modulus-m counter using a given msi

45、 modulus-n counter.,1. if mn, one msi device is needed.,2. if mn, more than one msi device is needed.,108,8-4-3 sequential logics design using msi counter,1. mn,skip n-m states,two methods: (1) implement it using the clear (reset) input (generally the clear input is asynchronous). (利用清零端，反馈归零法) (2)

46、implement it using the preset input. (some of the preset input are asynchronous, and others are synchronous) (利用预置端，置数法),109,8-4-3 sequential logics design using msi counter,momentary/astable state (瞬态), not included in the valid cycle. 异步清零，瞬态不包括在有效循环中,preset the states at any state 可在任意状态下进行预置 同步预置没有瞬态，异频预置有瞬态。,110,8-4-3 sequential logics design using msi counter,only when both of ep and et are active, is the counter enabled (in counter operation).,ex. 1 implement a modulus-6 counter using 74160. logic function table for 74160,clear inpu