CPLD课程设计交通灯程序

1、LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY jiaotongdeng IS PORT( clk_in:in std_logic; -4MHz rst:in std_logic;-复位信号 light:out std_logic_vector(7 downto 0); -RYG_main,RYG_gene spk:out std_logic; LED7S0:out STD_LOGIC_VECTOR(6 downto 0); LED7S1:out STD_LOGIC_VECTO

2、R(6 downto 0); LED7S2:out STD_LOGIC_VECTOR(6 downto 0); LED7S4:out STD_LOGIC_VECTOR(6 downto 0) ); END jiaotongdeng; ARCHITECTURE ARC OF jiaotongdeng IS type states is(green_red,yellow_red,red_green,red_yellow); signal state:states:=green_red; signal nextstate:states; signal data0:integer range 0 to

3、 9; signal data1:integer range 0 to 9; signal data2:integer range 0 to 9; signal data3:integer range 0 to 9; signal clock_buffer:std_logic; signal count_time:integer range 0 to ; signal clk:std_logic; signal sec0:integer range 0 to 9; signal sec1:integer range 0 to 3; signal sec2:integer range 0 to

4、9; signal sec3:integer range 0 to 3; BEGIN spk=0; frequent:process(clk_in) begin if clk_inevent and clk_in=1 then if count_time= then count_time=0; clock_buffer=not clock_buffer; else count_time=count_time+1; end if; end if; clklight=; nextstate=yellow_red; data0=5; data1=0; data2=5; data3light=; ne

5、xtstate=red_green; data0=4; data1=2; data2=9; data3light=; nextstate=red_yellow; data0=5; data1=0; data2=5; data3light=; nextstate=green_red; data0=9; data1=3; data2=4; data3=3; end case; end process; time:process(rst,clk) -记时状态 begin if rst=0 then -复位 sec0=9;sec1=3;sec2=4;sec3=3; elsif rising_edge(

6、clk) then if(sec0=0 AND sec1=0) or (sec2=0 AND sec3=0)then state=nextstate; sec0=data0; sec1=data1; sec2=data2; sec3=data3; else if sec2=0 then sec2=9; sec3=sec3-1; else sec2=sec2-1; end if; if sec0=0 then sec0=9; sec1=sec1-1; else sec0 LED7S0 LED7S0 LED7S0 LED7S0 LED7S0 LED7S0 LED7S0 LED7S0 LED7S0 LED7S0 LED7S3 LED7S3 LED7S3 LED7S3 LED7S2 LED7S2 LED7S2 LED7S2 LED7S2 LED