东南大学POC设计报告(附源程序vhdl)

1、Computer Organization and ArchitectureCourse DesignA parallel output controllerPOCSchool of Information Science and EngineeringSoutheast University2012-3-12CONTENTS1. Purpose22. Tasks23. Top-Level Structure3ComponentsInputsOutputs .POCs inside signals4. Input Waveforms65. Simulation results71) Basic

2、 function.82) abnormal conditions 6. Conclusions and Discussions97. Appendix10A Parallel Output Controller POC1. Purpose:The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Alteras Maxplus II EDA tool is

3、 recommended and provided for simulation. Please refer to William Stallings “Computer Organization and Architecture, Designing for Performance”, P.6575; P.185190.2. Tasks:POC is one of the most common I/O modules, namely the parallel output controller. It plays the role of an interface between the c

4、omputer system bus and the peripheral (such as a printer or other output devices).Figure 1 shows the connecting of a printer to the system bus through the POC. The communication between POC and the printer is controlled by a “handshake” protocol illustrated in Figure 2.The handshaking process is des

5、cribed as follows: When the printer is ready to receive a character, it holds RDY=1.The POC must then hold a character at PD (parallel data) port and produce a pulse at the terminal TR (transfer request). The printer will change RDY to 0, take the character at PD and hold the RDY at 0 until the char

6、acter has been printed (e.g. 5 or 10ms), then set RDY=1 again when it is ready to receive the next character. (Suppose the printer has only a one character “buffer” register, so that each character must be printed before the next character is sent).3. Top-Level Structure:Figure 3The overall connecti

7、on of the simulated printer and POC expressed in the top module formComponents:NameExplanationprintera simulated printer which has been simplified.POCThe parallel output controller.1)printerFigure 4 The integrated block of printerFigure 5 The internal circuit of the simulated printer module2)POCFigu

8、re 6 The integrated block of POCInputs:NameExplanationclkThe system clock for POC and printer.resetThe signal to restart POC and printer. In this experiment , reset=1 means POC and printer work normally, reset=0 means POC and printer restart to work.csChip Select. In this experiment, cs=1 means we c

9、hoose POC.rwRead/Write control. In this experiment, rw=0 means that POC reads data from the Process.a2.03-bit I/O address of POC. In this experiment, a=000 means the selection of BR in POC, and a=001 means the selection of SR in POCd7.08-bit data from CPU to POC for printing.Outputs:NameExplanationr

10、dyOutput of Printer which is used to indicate the Printer is ready to receive data from POC.trOutput of POC which is used to tell the Printer that data for transmission is prepared.pd7.0Output of POC. Data transferred to Printer is on pd port.irqInterrupt request terminal. POC sends a bit to CPU to

11、ask for an interruption for printing. It is pulled low when SR0=SR7=1.POCs inside signals:SR0: ready flag bit, SR0=1 means the POC is ready to receive data from Process SR7: interrupt enable bit, is used to enable or disable interrupt requests from POC. If SR0=1, then POC will interrupt when it is r

12、eady to receive a character (i.e. when SR7=1). If SR0=0,then POC will not interrupt.4. The Simulation Input WaveformsFigure 7 input waveformsDesign description:(1) The clock is set as 10per cycle, end time is 1ms; (2) reset=0 from 0 to 20. When we want to POC and printer work normally, we must set r

13、eset as 0 at first.(3) The d7.0 is set as sequential numbers increment by 1.(4) pd7.0 represents the parallel data port of POC. (5) irq, rdy, tr are output signals, depend on the present period.5. Simulation results1) basic functionWaveforms RecordP1P3P2P1Figure 7 basic function of the systemExplana

14、tionPeriod 1(P1): The printer has printed the former data, the POC is ready to receive new data. The data is transformed into BR.Signals: (a) reset=1 and resets event means POC and printer begin to work normally and SR7=1;(b) When a=000 and cs=1 and rw=0, SR0=1, then irq=0.(c) rdy =1 which means the

15、 printer is ready for a new transmission.Period 2(P2): the printer is receiving the data from POC. The POC must then hold a character at pd7.0 port.(a) SR0=SR7=0, then irq=1, means the POC is busy .(b) POC produce a pulse at the terminal tr. tr=1.(c) the data is ready to be printed and rdy=0,Period

16、3(P3): the printing period until the printer finished printing.Signals:(a) as we can see, this period last 5 clock cycles. If the data has not been finished printed , it will remain to stay in this period. If the printer finished printing ,it will come into the period 1.(b) rdy=0 remained as the for

17、mer period。(c) tr=0, when the printer is working or there is no data in PD port, tr will not be 1.2) abnormal conditions:cs=0) cs=0Waveforms RecordFigure 8 waveforms record when cs=0ExplanationAs we can see, when the POC works normally, the pd7.0 is 9, illustrated in figure 7. In figure 8, we set cs

18、=0at 70us to disable the POC works, then the pd7.0 becomes 10.)rw=1Waveforms Record rw=1 Figure 9 waveforms record when rw=1ExplanationIn figure 9, as we can see.When we set rw=1, the POC will not read datas from the Process. Until rw=0,the POC read data 28 into POC, and pd7.0 port is 28.6. Conclusi

19、ons and Discussions:1. According with the simulation results, the design has already reached the demand of the task.2. As an interface between the computer system bus and the print , POC designed in this experiment works well and efficiently.3. Characteristics of my design: simple, logic, stable, an

20、d fast.4. Something learned from this experiment:1) To use the EDA software Quartus II more deftly.2) To become more familiar to the VHDL language.3) The theory of how I/O modules work with CPU and external devices is completely mastered.4) To learn how to solve a whole project and how to write a de

21、sign report.5. Improvement of my design:Improve programs to examine the end of a serial data. In order to stop the POC working when all the data has been printed. 7. Appendix:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY POC IS PORT(clk,rw,cs,reset,rdy: IN STD_LOGIC; d: IN STD_LOGIC_VECTOR(7 downto 0); a: IN STD_LOGIC_VECTOR(2 downto 0); tr,irq: OUT STD_LOGIC; pd: OUT STD_LOGIC_VECTOR(7 downto 0);END POC;ARCHITECTURE BEHAVE OF POC ISSIGNAL SR: STD_LOGIC_V