2008-2009数字电路半期试题

1、系别 班次 学号 姓名 .密封线以内答题无效电子科技大学二零零八年至二零零九学年第二学期“数字逻辑设计及应用”课程考试题（半期）（120分钟） 考试日期2009年4月25日一二三四五六七八九十总分评卷教师I. TO FILL YOUR ANSWERS IN THE “ ” (4 X 10=40)1. 26.125 10 = 1A.2 16 2. (7A.C4)16 = ( 172.61 )8 .3. If X10 = -57，then Xsigned-magnitude = 10111001 2， ( Assumed the number system is 8-bit long ).4. I

2、f the signed-magnitude representation is（101101）2 for one number, then its 8-bit twos complement representation is( 11110011 )2. 5. If number A twos-complement =11111001 and B twos-complement=11010101, calculate A-B twos-complement and indicate whether or not overflow occurs. A-B twos-complement= 00

3、100100 , overflow NO 6. The binary number code is (1110101)2, then its corresponding Gray code is ( 1001111 ).7. The unused CMOS NAND gate inputs should be tied to logic (_1_) or another input. FABT2T1T4T3+EDFig.18. A CMOS circuit is shown as Fig1，its logic function F =(_(AB)_). (positive logic)9. I

4、f ，then dual expression(_). 10. If F=ABCD(1,6,8,10, 13)，then its invert function expression isABCD (_0,2,3,4,5,7,9,11,12,14,15_).II. Give your answers whether the statements are true or false(2*5=10)1. ( F ) If AB=AC is true for logic equation，then B=C is true.2. ( F ) A product expression for all m

5、interms of a logic function must be 1.3. ( T ) If a logic function ，then its inverse funcation .4. ( T ) when inputs is one “1” and 1000 “0” for XOR gate, then output is “1”.5. ( T ) A properly designed two-level sum-of-products (AND-OR) circuit has no static-0 hazards.III. there is only one correct

6、 answer in the following questions.(3 X 10=30)1. For a logical function, which representation as follows is one and only（唯一）. ( C )A) logic expression B) logic diagram C) truth table D) timing diagram2. The following logic expressions, the hazard-free one is ( D ).A) F=BC+AC+AB B) F=AC+BC+ABC) F=AC+

7、BC+AB+AB D) F=BC+AC+AB+BC+AB+AC3. The output signal of ( A ) circuit is 1-out-of-M code.A) binary decoder B) binary encoder C) seven-segment decoder D) decade counter4. The logic equation for a 2-input,1-bit multiplexer is F=AC+BC. If we want to build a two-input OR gate（F=X+Y）with this multiplexer

8、, show how to tie the input A, B and C? ( A ). A). The input A should be tied to logic“1”, B to X, and C to Y. B). The input A should be tied to X, B to logic “0” and C to Y. C). The input A and B should be tied together to X, and C to Y. D). The input A should be tied to logic “0”, B to X, and C to

9、 Y. 5. For a NAND gate in positive logic, if negative logic is adopted，then NAND gate will be changed to（ D ）。 A). NXOR gate B). NAND gate C). OR gate D). NOR gate6. A waveform of a 2-variable inputs logic gate is as the following, please judge this is ( C ) logic gate waveform. A) a NAND B) a NOR C

10、) an XNOR D) an AND ABF7. If we want to use an XNOR gate as an Inverter (NOT gate), then the inputs of A and B should connect as the ( B ) . A) one of the A and B connect to 1 B) one of the A and B connect to 0C) A and B connect together D) cant realize 8. Given ，the complement of F: =(_B_). A). A+(

11、BC)+(D+E) B). AB+AD+AC+DE C). AB+AC+D D). (A+B+C+E)D9. A circuit is consisted by one chip of 74X138 and one nand gate The logical function F(U,V,W,X,Y) =（ C ）. A). VYUWX（0,1,2,3,5,6,7） B). VYUWX（1,2,3,4,5,6,7） C). VY(U+W+X) D). VY(U+W+X)10. The circuit is shown as below. Assume that the propagation

12、delay of each gate is one . There are four timing diagrams, the ( C ) is correct.IV. Combinational Circuit Analysis And Design: 201. Build a 4-to-16 decoder with an enable input using 74x138, no inverter is used. 6每错一处连接扣0.5分，扣完6分为止。2. Write the minterm list expression for F=W+XZ+XY. 4 F=WXYZ( 5,6,7

13、,8,9,10,11,12,13,14,15 )每错一项连接扣0.4分，扣完4分为止。3. Design a combinational circuit with 4-bit inputs (Y3Y2Y1Y0) and 4-bit output (B3B2B1B0) to convert the excess-3 BCD code to 8421-BCD code. 10a). Write the function table (the truth table)b). Write the output logic functions for B2 and B0(with the minimal cost). a) The function table:INPUTSOUTPUTSY3Y2Y1Y0B3B2B1B00000dddd0001dddd0010dddd00110000010000010101001001