仪表放大器的内部构造 英文翻译版讲解

1、仪表放大器的内部构造一种简单的可实现放大功能的减法运算放大器图21 由运放A1组成的差分放大器功能结构图由图21我们可以看出，这是一种提高差模增益的最简单最实用的方法。如果R1=R3、R2=R4Vout=（VIN2-VIN1）尽管这种集成放大电路具有放大功能，而且在放大差模信号的同时可抑制共模信号，但他仍然存在着局限性。首先，反相输入阻抗太低而且不相等，在放大电路中，运方A1的输入阻抗为100K,而运方A2的输入电阻为200K，是A1的两倍。所以，当在一输入端加正电压而另一端接地时，由于输入电阻获得的电压不同而导致电流不同（信号源电阻上电流的不同会导致共模抑制比的降低）。此外，这个电路要求电阻

2、对R1/R2和R3/R4之间有非常相近的匹配，否则，每个输入端的增益就会不同这就会直接影响共模抑制比。例如，增益为1，所有等价电阻中即使有一个电阻出现0.1的匹配误差，也会使共模抑制比降到66dB的水平，阻值每偏差100共模抑制比就会降低6dB。尽管存在这些问题，这种通常被称为差分放大器或减法器的基本放大电路，作为构建模块，经常应用于那些高性能放大器中。作为一个具有独立功能的电路，差分放大器在影像设备和其他高速设备或具有低频率高共模抑制比的设备中具有非常高的实用性。在具有高共模电压的电路中，输入电阻用来分压及用作放大器的保护电路。某些通用差分放大器，如具有模拟装置的AD620，就在其设计中使用

3、了经过简单变换的差分放大器，这就使得集成电路可以处理比其本身电压还要高的共模输入电压。例如，当电源提供15V的电压时，AD620能以高达270V的共模电压来放大信号。在差分放大电路的前面增加一个具有高输入阻抗的缓冲放大器，可以有效地提高仪表放大器的性能，电路图如图22所示。图22具有缓冲电路的差分放大器因为放大电路具有很高的输入阻抗，所以，信号源的输入阻抗对放大电路的共模抑制比影响不大。用两个运方组成一个具有两输入端的缓冲放大器是相当合适的，因为两个运方不仅可以改善电路的温度，而且可以节省电路板空间，尽管电阻值不同，但这一电路和图23所示电路有着相同的放大功能。图23带有控制增益的缓冲放大器结

4、构的差分放大器图23所示是经过进一步改进的电路，现在输入缓冲电路用来控制电路的增益，使电路具有更高的灵活性。如果电阻R5R8,R6=R7,并且前面的电阻R1=R3,R2=R4,那么Vout（）(1)当图23所示电路中运方A1和A2同等的提高他们的差模增益时，共模增益也会随之提高。三运方放大电路图24所示电路图为放大电路的改进版，并且已经成为仪表放大器中最受欢迎的配置，这一经典运算放大电路是图23所示电路智能化的改进，同以前的电路一样，图24所示电路中的运方A1和A2用来缓冲输入电压。但是，在电路配置中，将电阻R连接在两个缓冲放大电路之间，来代替电阻R和R，这样在电阻R上就会出现差模电压（因为在

5、两放大器连接点处的电压与它的正极输入电压是相等的）。因为放大器的输入电压（在运方A1和A2的输出端）分别不同的分担在电阻R R和R三个电阻之上，所以差模增益可以仅由电阻R来改变。图24典型三运放结构的仪表放大器用这种连接方法还有另一个优势：一旦差分放大电路设置好了与之匹配的电阻，那么改变增益时不需要匹配其他电阻。如果电阻R5 = R6、 R1 = R3,、R2 = R4。那么Vout= (VIN2 VIN1) (1 + 2)因为电阻RG两端电压等于VIN,通过电阻RG的电流I=。所以，运方A1和A2控制着放大电路的增益和输入信号的放大。但是，当在放大器的输入端加上共模电压时，由于电阻RG两端的

6、电压相等，电阻上将没有电流通过。因为没有电流通过RG，(也没有电流通过R5和R6),运方A1和A2起到了。所以，共模信号在通过放大器时会受到抑制，而差模信号会放大为原来的(1 + )倍。理论上，这意味着，使用者可以在不增加共模增益和误差的情况下获取想要得到的增益（由电阻RG决定的）。因为差模信号得到放大，而共模信号没有放大，共模抑制比得到提高。因此，在理论上说，共模抑制比和增益成正比增加一个非常有用的特点。最后，由于电路配置成对称性，输入放大器产生的的共模误差会在输出放大器那里得到补偿。这包括像共模抑制比频率这样的误差。这些特性说明了这种配置为什么这样流行。三运放的设计思路对于构建三运放结构放

7、大电路来说，以下两种选择都是可行的:使用FET（场效应晶体放大器）或具有双端输入运算放大器。FET放大器的偏置电流很低，并且非常适用于具有高输入阻抗()的信号源。相对于双极放大器来说，FET放大器具有较低的共模抑制，较高的补偿电压和补偿电流，在给定电压范围的情况下也可以提供更高摆率。输出感测端和参考端的设置使得用户可以改变反馈回路和地线连接，输出感测端可以由外部驱动，用来伺服应用和调节运方A3的增益。同样，参考终端的设置使得运方A3可以运用外部的补偿电压。为能正常的运转，将输出感测端和输出终端连接在一起，就像参考终端和接地端一样。双极输入放大器比起FET放大器，具有较高的共模抑制、较低的输入补

8、偿电压和电流。超级双极输入放大器兼有众多FET和双极放大器的优点，而且比之FET有着更低的偏置电流。那些粗心的设计者运用三运方设计的作品都有一个共同的缺陷，那就是当运放在高增益状态运行时会出现共模电压幅值减小的情况。图25是三运放工作在增益为1000时的电路图。在这一例子中，当输出放大器提供单一增益时，运放A1和A2的增益为1000。这就意味着每个运放的输出端电压为输入电压峰峰值X1000再加上任一输入端的共模电压（不管差模信号和共模信号是否以单一增益通过）的0.5倍。所以，如果一个10mv的差模信号作用于输入端，加上共模电压，输出电压为5V，A2的输出电压为-5V。如果给放大器加一个15V电

9、压，通常情况下会消减为7V或7V多一点。因此，允许8V的共模电压通过但不能超过12V，这是一种非常典型的单一增益，高增益或是低供给电压会进一步减小共模电压幅值。图25具有减小共模抑制功能的三运放仪表放大器基本的两运放仪表放大器图26所示电路是一种典型的两运放仪表放大器，它具有明显的优势，只需要两个而不是三个运放。并且低耗能低功耗。但是，同三运放的设计相比，两运放放大电路的非对称式拓扑结构导致了几个不利结果，最糟糕的就是低交流共模增益，这就使得这个电路没多少利用价值。电路的调节作用是 Vout（）(1)（因为R=R、R=R）此放大器的输入阻抗很高，而且是对称的，所以信号源的输出阻抗可以不对称。放

10、大电路的输入偏置电流由两个运放的同相输入端对输入电流的需求所决定，而且，输入电流相当低，这是很典型的。这种放大电路也有不少弱点。首先，对单一的增益不能很好的控制；其次，因为电路的增益相当低，使得共模电压幅值增大；再者，共模抑制也很低，这是由运放输入端电压Vin1和Vin2相位变化不相等引起的，输入信号只有在通过运放A1后才能和运放A2输入端电压Vin2相减，所以，运放A1输出电压会有些微的延迟或有部分电压在传输中损耗。图26具有两运放结构的仪表放大器两运放仪表放大器电路通常的最小增益是5，因为这样就使得电路对交流共模输入电压幅值要求很宽松，并且，其充足的带宽可满足很多方面的应用。双输入端放大器

11、的使用使得共模电压幅值扩展到了-VS，这样就增大了其输出电压的范围(输出值可从+VS到-VS)。表21显示了图26所示电路的增益。并且，为几个共同电路增益给出了1%的电阻值。表21 图26所示电路图的运放A1和A2的可控性增益及部分电阻值表单向供电放大器的两运放共模增益的设计思路当从图27所示的两运放仪表放大器电路的参考输入端观察时，我们会发现，这一电路仅是两个变换器的串联。假定两个信号输入端的电压都是0，那么，输出电压 Vo1=-V加于电压V上的正极电压可能会趋于控制放大器负极的输出电压。如果放大器由单向电源（0到4VS）控制，那么，这种情况就不大可能会出现。图27 两运放仪表放大器结构图

12、从运放A1的输出端到整个电路的输出端，即A2的输出端，电压增益等于 V=-V从电压V到V的增益是这两个增益的共同作用结果，等于 V=-V（-）（因为R=R、R=R）所以，正如所预料的，电阻增益为+1，值得注意的是，两个变换器的存在导致了这样的结果，而在三运放仪表放大电路中，其参考输入端的同相信道起着同样的作用。和三运放一样，两运放放大电路也可通过单向供电和参考电压的选择来限制共模电压的幅值。图28运用2.5V参考电压的两运放仪表放大器输出电压的范围限制电路图图28是由5V电源电压控制的两运算器放大电路图。在本例中参考输入端输入电压为2.5V，对于0V的差模输入电压和0到5V的任何输入共模电压，

13、理想情况下，输出电压应该是2.5V。当共模电压从2.5V向5V递增时，运放A1的输出电压为 Vo1=VCM+(VCM-VREF)（R2/R1）在本例中，V=2.5V，R2/R1=1/4，当VcM=4.5V时，A1的输出电压将会达到5v，共模电压会明显增加。事实上，运放A1和A2的输入电压幅值得局限性可能会将放大器共模电压幅值限制在4.5V内。同样，当共模电压从2.5v降到0时，运放A1的输出电压由0.5V的共模电压降为0。很明显，运放A1的输出电压并不比反向输入或放大器输出电压向负电压方向拓展多多少。这种反向供给或运放在单项供电时的输出电压为0。对于AD620内的单片式两运放仪表放大器，即使最

14、为恰当的设计正共模电压幅度仍会为利于控制而降为0。另外，可能更为糟糕的是，同三运放仪表放大器设计相比，两运放仪表放大器设计标准的局限性，对其获得高交流共模抑制是一个内在的阻碍，这一局限性源于两运放共模信道中固有的不平衡状态。假定一正弦电压以FCM的频率输入V和V（图28），理想情况下，若独立频率FCM至少在正常交流电压频率范围之内4050HZ，那么，最终交流输出电压的幅值应该是0V（共模误差），电压传输将成为大量共模干扰的源泉。直接供给VIN2的共模电压和被运放A1及经电阻R1、R2组成的伴随运放A1的增益电路放大后的共模电压之间，在到0伏时有着瞬间的差别。如果交流共模误差为0，运放A1和由其

15、电阻R3、R4组成的增益电路一定会出现这种瞬间的差别。任何交流共模误差（假定这种微不足道的误差来自运放本身的共模抑制比）都能通过调整R1、R2、R3、R4的比例来消除，进而获得如下平衡,R1=R4、R2=R3。但是，任何由放大器A1引入的相位移动都会导致电压VO1的相位略微滞后于VIN2的直接供给电压的相位。这种相位上的不同步会导致VO1和VIN2之间瞬间的不同(传输媒介)，即使产生两电压的放大器正处于其最理想的水平，这就会使得电路的输出电压Vout的频率依赖于共模误差电压。进而，这种交流共模误差将会随共模频率线性的增加，因为通过运放A1的相位移动共模误差会随频率径直增加，事实上，因为频率远少

16、于运放A1闭环频带的1/10，共模误差（涉及到放大器的输入）可以在输出电压Vout的共模误差电压那与A1闭环带宽接近，由以下公式可看出 %CMError=(100%)=% G是差模增益本例中为5。例如，如果运放A1有一个100KHZ的闭环增益（对微电放大器来说是相当典型的），当通过R1和R2来控制增益设置并且共模频率为100HZ时，那么%CMError=100HZ/100KHZ =0.1%1%的共模误差等效于60dB的共模抑制，所以，在本例中即使改变电路获得100dB的交流CRM，这只能对不到1HZ的频率起作用。AD627同相放大器是两运放仪表放大器中较为先进的产品，它克服了交流共模抑制的局限

17、性，正如图29所示，AD627可以在8KHZ时保持80dB的CRM（增益为1000），即使运放A1和A2的频带只有150KHZ。图29仪表放大器AD627的共模抑制和频率比率图用于减法器中的四个电阻通常处于集成电路的内部并且有很高的阻值。 很典型的，高共模电压的差分放大器用输入电阻进行电压的调节.所以，差模信号和共模信号电压是可调的，共模电压受到抑制，而差模电压就得到放大。INSIDE AN INSTRUMENTATION AMPLIFIERA Simple Op Amp Subtractor Provides an In-Amp FunctionThe simplest (but still

18、 very useful) method of implementing a differential gain block is shown in Figure 2-1.Figure 2-1. A 1-Op Amp IN-Amp Difference Amplifier Circuit Functional Block DiagramAlthough this circuit provides an in-amp function, amplifying differential signals while rejecting those that are common mode, it a

19、lso has some limitations. First, the impedances of the inverting and noninverting inputs are relatively low and unequal. In this example, the input impedance to VIN1 equals 100 k, while the impedance of VIN2 is twice that, at 200 k. Therefore, when voltage is applied to one input while grounding the

20、 other, different currents will flow depending on which input receives the applied voltage. (This unbalance in the sources resistances will degrade the circuits CMRR.)Furthermore, this circuit requires a very close ratio match between resistor pairs R1/R2 and R3/R4; otherwise, the gain from each inp

21、ut would be differentdirectly affecting common-mode rejection. For example, at a gain of 1, with all resistors of equal value, a 0.1% mismatch in just one of the resistors will degrade the CMR to a level of 66 dB (1 part in 2,000). Similarly, a source resistance imbalance of 100欧 will degrade CMR by

22、 6 dB.In spite of these problems, this type of bare bones in-amp circuit, often called a difference amplifier or subtractor, is useful as a building block within higher performance in-amps. It is also very practical as a standalone functional circuit in video and other high speed uses, or in low fre

23、quency, high common-mode voltage (CMV) applications, where the input resistors divide down the input voltage as well as provide input protection for the amplifier. Some monolithic difference amplifiers such as Analog Devices AD629 employ a variation of the simple subtractor in their design. This all

24、ows the IC to handle common-mode input voltages higher than its own supply voltage. For example, when powered from a 正负15 V supply, the AD629 can amplify signals with common-mode voltages as high as正负270 V.Improving the Simple Subtractor with Input BufferingAn obvious way to significantly improve pe

25、rformance is to add high input impedance buffer amplifiers ahead of the simple subtractor circuit, as shown in the 3-op amp instrumentation amplifier circuit of Figure 2-2.Figure 2-2. A Subtractor Circuit with Input BufferingThis circuit provides matched, high impedance inputs so that the impedances

26、 of the input sources will have a minimal effect on the circuits common-mode rejection. The use of a dual op amp for the 2-input buffer amplifiers is preferred because they will better track each other over temperature and save board space. Although the resistance values are different, this circuit

27、has the same transfer function as the circuit of Figure 2-3.Figure 2-3. A Buffered Subtractor Circuit with Buffer Amplifiers Operating with GainFigure 2-3 shows further improvement: now the input buffers are operating with gain, which provides a circuit with more flexibility. If the value of R5 = R8

28、 and R6 = R7 and, as before, R1 = R3 and R2 = R4, thenVOUT = (VIN2 VIN1) (1 + R5/R6) (R2/R1)While the circuit of Figure 2-3 does increase the gain (of A1 and A2) equally for differential signals, it also increases the gain for common-mode signals.The 3-Op Amp In-AmpThe circuit of Figure 2-4 provides

29、 further refinement and has become the most popular configuration for instrumentation amplifier design. The classic 3-op amp in-amp circuit is a clever modification of the buffered subtractor circuit of Figure 2-3. As with the previous circuit, op amps A1 and A2 of Figure 2-4 buffer the input voltag

30、e. However, in this configuration, a single gain resistor, RG, is connected between the summing junctions of the two input buffers, replacing R6 and R7. The full differential input voltage will now appear across RG (because the voltage at the summing junction of each amplifier is equal to the voltag

31、e applied to its positive input). Since the amplified input voltage (at the outputs of A1 and A2) appears differentially across the three resistors R5, RG, and R6, the differential gain may be varied by just changing RG.Figure 2-4. The Classic 3-Op Amp In-Amp CircuitThere is another advantage of thi

32、s connection: once the subtractor circuit has been set up with its ratio-matched resistors, no further resistor matching is required when changing gains. If the value of R5 = R6, R1 = R3, and R2 = R4, thenVout= (VIN2 VIN1) (1 + 2R5/RG)(R2/R1)Since the voltage across RG equals VIN, the current throug

33、h RG will equal (VIN/RG). Amplifiers A1 and A2, therefore, will operate with gain and amplify the input signal. Note, however, that if a common-mode voltage is applied to the amplifier inputs, the voltages on each side of RG will be equal and no current will flow through this resistor. Since no curr

34、ent flows through RG (nor, therefore, through R5 and R6), amplifiers A1 and A2 will operate as unity gain followers. Therefore, common-mode signals will be passed through the input buffers at unity gain, but differential voltages will be amplified by the factor (1 + (2 RF/RG). In theory, this means

35、that the user may take as much gain in the front end as desired (as determined by RG) without increasing the common-mode gain and error. That is, the differential signal will be increased by gain, but the common-mode error will not, so the ratio (Gain (VDIFF)/(VERR OR CM) will increase. Thus, CMRR w

36、ill theoretically increase in direct proportion to gaina very useful property. Finally, because of the symmetry of this configuration, common-mode errors in the input amplifiers, if they track, tend to be canceled out by the output stage subtractor. This includes such errors as common-mode rejection

37、 vs. frequency. These features explain the popularity of this configuration. 3-Op Amp In-Amp Design Considerations Two alternatives are available for constructing 3-op amp instrumentation amplifiers: using FET or bipolar input operational amplifiers. FET input op amps have very low bias currents and

38、 are generally well suited for use with very high (10E6欧) source impedances. FET amplifiers usually have lower CMR, higher offset voltage, and higher offset drift than bipolar amplifiers. They also may provide a higher slew rate for a given amount of power.The sense and reference terminals (Figure 2

39、-4) permit the user to change A3s feedback and ground connections. The sense pin may be externally driven for servo applications and others for which the gain of A3 needs to be varied. Likewise, the reference terminal allows an external offset voltage to be applied to A3. For normal operation, the s

40、ense and output terminals are tied together, as are reference and ground.Amplifiers with bipolar input stages tend to achieve both higher CMR and lower input offset voltage drift than FET input amplifiers. Super beta bipolar input stages combine many of the benefits of FET and bipolar processes, wit

41、h even lower IB drift than FET devices.A common (but frequently overlooked) pitfall for the unwary designer using a 3-op amp in-amp design is the reduction of common-mode voltage range that occurs when the in-amp is operating at high gain. Figure 2-5 is a schematic of a 3-op amp in-amp operating at

42、a gain of 1,000.Figure 2-5. A 3-Op Amp In-Amp Showing Reduced CMV RangeIn this example the input amplifiers, A1 and A2, are operating at a gain of 1,000, while the output amplifier is providing unity gain. This means that the voltage at the output of each input amplifier will equal one-half the peak

43、-to-peak input voltage X 1,000, plus any common-mode voltage that is present on the inputs (the common-mode voltage will pass through at unity gain regardless of the differential gain). Therefore, if a 10 mV differential signal is applied to the amplifier inputs, amplifier A1s output will equal +5 V

44、, plus the common-mode voltage, and A2s output will be 5 V, plus the common-mode voltage. If the amplifiers are operating from 15 V supplies, they will usually have 7 V or so of headroom left, thus permitting an 8 V common-mode voltagebut not the full 12 V of CMV which, typically, would be available

45、 at unity gain (for a 10 mV input). Higher gains or lower supply voltages will further reduce the common-mode voltage range.The Basic 2-Op Amp Instrumentation AmplifierFigure 2-6 is a schematic of a typical 2-op amp in-amp circuit. It has the obvious advantage of requiring only two, rather than thre

46、e, operational amplifiers and providing savings in cost and power consumption. However, the nonsymmetrical topology of the 2-op amp in-amp circuit can lead to several disadvantages, most notably lower ac CMRR, compared to the 3-opamp design, limiting the circuits usefulness.The transfer function of

47、this circuit isVOUT = (VIN2 VIN1) (1 + R4/R3)for R1 = R4 and R2 = R3Figure 2-6. A 2-Op Amp In-Amp CircuitTable 2-1. Operating Gains of Amplifiers A1 and A2 and Practical 1% Resistor Values for the Circuit of Figure 2-6Input resistance is high and balanced, thus permitting the signal source to have a

48、n unbalanced output impedance. The circuits input bias currents are set by the input current requirements of the noninverting input of the two op amps, which typically are very low.Disadvantages of this circuit include the inability to operate at unity gain, a decreased common-mode voltage range as

49、circuit gain is lowered, and poor ac common-mode rejection. The poor CMR is due to the unequal phase shift occurring in the two inputs, VIN1 and VIN2. That is, the signal must travel through amplifier A1 before it is subtracted from VIN2 by amplifier A2. Thus, the voltage at the output of A1 is slig

50、htly delayed or phase-shifted with respect to VIN1. Minimum circuit gains of 5 are commonly used with the 2-op amp in-amp circuit because this permits an adequate dc common-mode input range, as well as sufficient bandwidth for most applications. The use of rail-to-rail (single-supply) amplifiers wil

51、l provide a common-mode voltage range that extends down to VS (or ground in single-supply operation), plus true rail-to-rail output voltage range (i.e., an output swing from +VS to VS).Table 2-1 shows amplifier gain vs. circuit gain for the circuit of Figure 2-6 and gives practical 1% resistor value

52、s for several common circuit gains.2-Op Amp In-AmpsCommon-Mode DesignConsiderations for Single-Supply OperationWhen the 2-op amp in-amp circuit of Figure 2-7 is examined from the reference input, it is apparent that it is simply a cascade of two inverters. Figure 2-7. The 2-Op Amp In-Amp Architectur

53、eAssuming that the voltage at both of the signal inputs, VIN1 and VIN2, is 0, the output of A1 will equalVO1 = VREF (R2/R1)A positive voltage applied to VREF will tend to drive the output voltage of A1 negative, which is clearly not possible if the amplifier is operating from a single power supply v

54、oltage (+VS and 0 V). The gain from the output of amplifier A1 to the circuits output, VOUT, at A2, is equal toVOUT = VO1 (R4/R3)The gain from VREF to VOUT is the product of these two gains and equalsVOUT = (VREF (R2/R3)(R4/R3)In this case, R1 = R4 and R2 = R3. Therefore, the reference gain is +1, a

55、s expected. Note that this is the result of two inversions, in contrast to the noninverting signal path of the reference input in a typical 3-op amp in-amp circuit. Just as with the 3-op amp in-amp, the common-mode voltage range of the 2-op amp in-amp can be limited by single-supply operation and by

56、 the choice of reference voltage. Figure 2-8 is a schematic of a 2-op amp in-amp operating from a single 5 V power supply. The reference input is tied to VS/2 which, in this case, is 2.5 V. The output voltage should ideally be 2.5 V for a differential input voltage of 0 V and for any common-mode vol

57、tage within the power supply voltage range (0 V to 5 V).Figure 2-8. Output Swing Limitations of 2-Op Amp In-Amp Using a 2.5 V ReferenceAs the common-mode voltage is increased from 2.5 V toward 5 V, the output voltage of A1 (VO1) will equalVO1 = VCM + (VCM VREF) (R2/R1)In this case, VREF = 2.5 V and

58、R2/R1 = 1/4. The output voltage of A1 will reach 5 V when VCM = 4.5 V. Further increases in common-mode voltage obviously cannot be rejected. In practice, the input voltage range limitations of amplifiers A1 and A2 may limit the in-amps common-mode voltage range to less than 4.5 V.Similarly, as the common-mode voltage is reduced from 2.5 V toward 0 V, the output voltage of A1 will hit zero for a VCM of 0.5 V. Clearly, the output