多周期MPIS指令集设计

1、 指令类型31:2625:2120:1615:1110:65:0r类型oprsrtrdshamtfunct含义nop00000000000000000000000000000000空操作addu000000rsrtrd00000100001加（不带溢出）subu000000rsrtrd00000100011减（不带溢出）and000000rsrtrd00000100100与or000000rsrtrd00000100101或xor000000rsrtrd00000100110异或nor000000rsrtrd00000100111或非sllv000000rsrtrd00000000100逻辑左

2、移变量srlv000000rsrtrd00000000110逻辑右移变量i类型oprsrtimmediatebltz000001rs00000immediate小于0转移beq000100rsrtimmediate相等转移bne000101rsrtimmediate不相等转移addi001000rsrtimmediate加立即数andi001100rsrtimmediate与立即数ori001101rsrtimmediate或立即数lw100011rsrtimmediate取字sw101011rtrtimmediate存字j类型opaddressj000010address无条件跳转综述：本设

3、计选用了如下指令，基于此设计出了单周期mips处理器，并在单周期的基础上添加了5级流水线设计出了带五级流水线的mips处理器。 第一部分 单周期mips处理器一、 代码 - module name: top_mips - behavioral 顶层模块-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity top_mips is port( reset: in std_logic; clk: in std_logic; ov: ou

4、t std_logic);end top_mips;architecture behavioral of top_mips is signal s_pc:std_logic_vector(31 downto 0); -pc输入 signal s_pc_i:std_logic_vector(31 downto 0); -pc输出signal s_command:std_logic_vector(31 downto 0); -指令signal s_add1_pc:std_logic_vector(31 downto 0); -pc+1值signal s_shift:std_logic_vector

5、(27 downto 0); -指令低26位左移2位后值signal s_jump_pc:std_logic_vector(31 downto 0); -绝对跳转signal s_regdst:std_logic; -控制信号 signal s_jump: std_logic;signal s_branch: std_logic;signal s_memread: std_logic;signal s_memtoreg: std_logic;signal s_aluop: std_logic_vector( 3 downto 0);signal s_memwrite:std_logic;sig

6、nal s_alusrc:std_logic;signal s_regwrite: std_logic;signal s_opa:std_logic_vector(31 downto 0); -alu操作数signal s_opb:std_logic_vector(31 downto 0); -alu操作数signal s_reg_data:std_logic_vector(31 downto 0); -寄存器读出的第二个数据signal s_imm_data:std_logic_vector(31 downto 0); -低16位符号扩展后signal s_zero:std_logic; s

7、ignal s_alu_result:std_logic_vector(31 downto 0);signal s_branch_pc:std_logic_vector(31 downto 0); -条件跳转signal s_1orbranch:std_logic_vector(31 downto 0); signal s_ram_data:std_logic_vector(31 downto 0);signal s_wr_data:std_logic_vector(31 downto 0);signal s_mux:std_logic;signal s_alu_ctrl:std_logic_

8、vector(3 downto 0);signal s_aimreg_addr:std_logic_vector(4 downto 0); 写寄存器堆的地址 component pc is -pc指针模块 port( reset: in std_logic; clk: in std_logic; pc_i: in std_logic_vector(31 downto 0); pc_o:out std_logic_vector(31 downto 0); end component; component memory is -指令存储器 port( reset: in std_logic; me

9、m_adr: in std_logic_vector(31 downto 0); mem_out: out std_logic_vector(31 downto 0); end component; component reg_32bit_array is -寄存器堆 port( reset: in std_logic; clk: in std_logic; wr_en: in std_logic; addr_wr: in std_logic_vector(4 downto 0); addr1_rd: in std_logic_vector(4 downto 0); addr2_rd: in

10、std_logic_vector(4 downto 0); reg_data_i: in std_logic_vector(31 downto 0); reg_data1_o: out std_logic_vector(31 downto 0); reg_data2_o: out std_logic_vector(31 downto 0); end component; component ram is -数据存储器 port( reset :in std_logic; clk :in std_logic; rd_en :in std_logic; wr_en:in std_logic; ad

11、dr: in std_logic_vector(5 downto 0); data_i: in std_logic_vector(31 downto 0); data_o: out std_logic_vector(31 downto 0); end component; component fsm is - 指令译码器 port( command:in std_logic_vector(5 downto 0); regdst:out std_logic; jump : out std_logic; branch: out std_logic; memread: out std_logic;

12、memtoreg: out std_logic; aluop: out std_logic_vector(3 downto 0); memwrite:out std_logic; alusrc:out std_logic; regwrite:out std_logic); end component; component alu_ctrl is -alu控制单元 port( funct_i:in std_logic_vector(5 downto 0); aluop_i:in std_logic_vector(3 downto 0); alu_ctrl_o: out std_logic_vec

13、tor(3 downto 0); end component; component alu is -alu port( op_a,op_b: in std_logic_vector(31 downto 0); alu_ctrl_i:in std_logic_vector(3 downto 0); zero:out std_logic; result:out std_logic_vector(31 downto 0); end component; component add is - 加法器 port ( op_a,op_b: in std_logic_vector(31 downto 0);

14、 result: out std_logic_vector(31 downto 0); ov: out std_logic ); end component;begin s_shift=s_command(25 downto 0)&00; - 左移2位 s_add1_pc=s_pc+1; -pc+1 s_jump_pc=s_add1_pc(31 downto 28)&s_shift; -无条件跳转地址 s_mux=s_branch and s_zero; s_aimreg_addr=s_command(20 downto 16) when s_regdst=0 else s_command(1

15、5 downto 11); s_opb=s_reg_data when s_alusrc=0 else s_imm_data; s_1orbranch=s_add1_pc when s_mux=0 else s_branch_pc;s_pc_i=s_1orbranch when s_jump=0 else s_jump_pc; s_wr_data=s_alu_result when s_memtoreg=0 else s_ram_data; -expand s_imm_data reset, clk = clk, pc_i = s_pc_i, pc_o = s_pc); mips_memory

16、: memory port map( reset = reset, mem_adr = s_pc, mem_out = s_command); mips_regs: reg_32bit_array port map(reset = reset, clk = clk,wr_en = s_regwrite , addr_wr = s_aimreg_addr, addr1_rd = s_command(25 downto 21),addr2_rd = s_command(20 downto 16), reg_data_i = s_wr_data, reg_data1_o = s_opa,reg_da

17、ta2_o = s_reg_data); mips_ram: ram port map( reset = reset, clk = clk, wr_en = s_memwrite, rd_en = s_memread, addr = s_alu_result(5 downto 0), data_i = s_reg_data, data_o = s_ram_data); mips_fsm: fsm port map( command = s_command(31 downto 26), regdst = s_regdst, jump = s_jump , branch = s_branch, m

18、emread = s_memread, memtoreg = s_memtoreg, aluop = s_aluop, memwrite = s_memwrite, alusrc = s_alusrc, regwrite = s_regwrite); mips_aluctrl: alu_ctrl port map( funct_i = s_command(5 downto 0), aluop_i = s_aluop, alu_ctrl_o = s_alu_ctrl); mips_alu: alu port map( op_a = s_opa, op_b = s_opb, alu_ctrl_i

19、= s_alu_ctrl, zero = s_zero, result = s_alu_result); mips_add: add port map( op_a = s_add1_pc , op_b = s_imm_data, result = s_branch_pc, ov = ov);end behavioral;- module name: pc - behavioral pc模块-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;e

20、ntity pc is port( reset: in std_logic; clk: in std_logic; pc_i:in std_logic_vector(31 downto 0); pc_o:out std_logic_vector(31 downto 0);end pc;architecture behavioral of pc isbegin process(clk,reset,pc_i) begin if reset=1 then pc_o=x00000000; elsif (clkevent and clk=1) then pc_o=pc_i; end if; end pr

21、ocess;end behavioral;- module name: memory - behavioral 程序存储器模块-指令存储器 6432 -library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity memory is port( reset:in std_logic; mem_adr:in std_logic_vector(31 downto 0); mem_out:out std_logic_vector(31 downt

22、o 0);end memory;architecture behavioral of memory is type mem_data is array(0 to 63)of std_logic_vector(31 downto 0); - 指令存储器 signal rom_table: mem_data; begin process(reset,mem_adr,rom_table) begin if (reset=1) then rom_table=( - 将指令通过reset固化进去 00000000000000000000000000000000, - nop 00000000000000

23、000000000000000000, - nop 00000000001000100000100000100000, - add 00000000011000100001000000100010, - sub 00000000100001010001100000100100, - and 00000000110001110010000000100101, - or 00000001000010010010100000100110, - xor 00000001010010110011000000100111, - nor 00000001100011010011100000000100, -

24、 sllv 00000001110011110100000000000110, - srlv 00000111111000000000000000000010, - bltz 00000000000000000000000000000000, 00000000000000000000000000000000, 00010010001011110000000000000010, - beq 00000000000000000000000000000000, 00000000000000000000000000000000, 00010110010100110000000000000010, -

25、ben 00000000000000000000000000000000, 00000000000000000000000000000000, 00000110000000000000000000000010, - bltz 00000000000000000000000000000000, 00000000000000000000000000000000, 00010010001100010000000000000010, - beq 00000000000000000000000000000000, 00000000000000000000000000000000, 00010111111

26、000000000000000000010, - ben 00000000000000000000000000000000, 00000000000000000000000000000000, 00100010011111100000000011111111, - addi 00110010100111010000000000011001, - andi 00110110110111000000000000011000, - ori 10001100000110110000000000001111, - lw 10101100000101110000000000011111, - sw 000

27、01000000000000000000000011101, - j 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 000000000000000000000000000

28、00000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 000000000000000000000

29、00000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 000000000000000

30、00000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000, 00000000000000000000000000000000);mem_out = x00000000; else rom_table = rom_table ; mem_out = rom_table(conv_integer(mem_adr(5 downto 0); -指令存储器容量-不够，故只取低-6位 end if;end process;en

31、d behavioral;- module name: reg_32bit_array - behavioral 寄存器堆-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity reg_32bit_array is port( reset: in std_logic; clk :in std_logic; wr_en : in std_logic; addr_wr: in std_logic_vector(4 downto 0);

32、- 写寄存器 addr1_rd: in std_logic_vector(4 downto 0); - 1号读寄存器 addr2_rd: in std_logic_vector(4 downto 0); - 2号读拇嫫? reg_data_i: in std_logic_vector(31 downto 0); -要写入的数据 reg_data1_o: out std_logic_vector(31 downto 0); - 读数据1 reg_data2_o: out std_logic_vector(31 downto 0); - 读数据2 end reg_32bit_array;archi

33、tecture behavioral of reg_32bit_array is type regs_32bit is array(0 to 31) of std_logic_vector(31 downto 0);signal regs:regs_32bit;begin process(reset,clk,regs,addr_wr,addr1_rd,addr2_rd,reg_data_i,wr_en) begin if reset=1 then - reset all regs regs= ( -初值x00000000,x00000001,x00000002,x00000003, x0000

34、0004,x00000005,x00000006,x00000007, x00000008,x00000009,x0000000a,x0000000b, x0000000c,x0000000d,x0000000e,x0000000f, x00000010,x00000011,x00000002,x00000003, x00000014,x00000015,x00000006,x00000007, x00000018,x00000019,x0000001a,x0000001b, x0000001c,x0000001e,x0000001d,x0000001f); reg_data1_o=x0000

35、0000; reg_data2_o=x00000000; else reg_data1_o=regs(conv_integer(addr1_rd); -read op_a reg_data2_o=regs(conv_integer(addr2_rd); -read op_b if (clkevent and clk=1) then if wr_en=1 then regs(conv_integer(addr_wr)=reg_data_i; -writeend if; end if; end if; end process; end behavioral;- module name: ram -

36、 behavioral 数据存储器-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity ram is port( reset:in std_logic; clk:in std_logic; rd_en:in std_logic;wr_en:in std_logic;addr: in std_logic_vector(5 downto 0);-取地址数据的低5位（限于ram容量）data_i: in std_logic_vector

37、(31 downto 0);data_o: out std_logic_vector(31 downto 0);end ram;architecture behavioral of ram is type ram_array is array (0 to 63) of std_logic_vector(31 downto 0);-6432 signal ram_data: ram_array;begin process(reset,clk,addr,ram_data,data_i,wr_en,rd_en) begin if reset=1 then -reset data of ram. ra

38、m_data=( x00000000,x00000001,x00000002,x00000003, x00000004,x00000005,x00000006,x00000007, x00000008,x00000009,x0000000a,x0000000b, x0000000c,x0000000d,x0000000e,x0000000f, x00000010,x00000011,x00000012,x00000013, x00000014,x00000015,x00000016,x00000017, x00000018,x00000019,x0000001a,x0000001b, x0000001c,x0000001e,x0000001d,x0000001f, x