华南理工大学 2014年数字系统设计(全英)B卷

1、1. Multiple choice test（25=10 marks）1 . Which of the following statements on VHDL process is not true（ C ）Aa signal can be read in multiple processes;B. a signal can be assigned values for multiple times in a process, however, only the last assignment takes effect;Ca signal can be assigned values in

2、 different process;Da process can be triggered either by means of sensitivity list or by wait statement; 2. Which of the following statements is not true（ D ）A. The working frequency of a synchronous digital system shouldnt exceed the reciprocal (倒数) of its maximal delay;B. The working frequency of

3、a synchronous digital system is limited by the delay of its components.C. Asynchronous digital system is more efficient in terms of resources than synchronous system.D. Asynchronous digital system is more reliable than synchronous system.3. Which of the following statements on synthesis is not true（

4、 D ）A. Synthesis is a transformation process from one representation of the design to another representation form；B. Synthesis transforms the high level HDL to low level hardware netlist, which is produced according to FPGA/CPLD structure；C. Synthesis is usually limited by the surface and speed of t

5、he circuit；D. Synthesis is a mapping process from high level description to low level hardware representation. The mapping relationship is unique and the synthesis result is unique. 4. Which of the following statements on VHDL simulation&synthesis is not true:（ B ）A. the time delay following the aft

6、er statement cant be synthesized;B. A pulse signal cant propagate through the path if its duration is less than transport delay;C. For a VHDL signal, its initial value assigned in its declaration part is valid in simulation only; its ignored by the VHDL synthesis;D. Simulation is actually a process

7、of checking and verification;5. In state machine coding,（ A ）can save the resources for decoding and reduce the risk of illegal states at the price of more register resources: A . one-hot coding B. random coding C. natural binary coding D. gray code2. Short Q&A（ 102=20 marks）1、 The following figure

8、shows the critical path of a digital system. (10 marks)(1) Please give a brief explanation respectively for the timing parameters including tsu, thold, tc-q, tlogic(2) According the timing parameters in the figure, calculate the maximal delay max of the critical path (or the maximal working frequenc

9、y fmax of the system). Set up time： To ensure reliable operation, the input to a register must be stable for a minimum time before the clock edge (register setup time or tSU). if the time is not long enough, reliable operation can not be guaranteedHold time： To ensure reliable operation, the input t

10、o a register must be stable for a minimum time after the clock edge (register hold time or tH). if the time is not long enough, reliable operation can not be guaranteed. TcqThe register output then is available after a specified clock-to-output delay (tco or tcq).tlogicThe worst combinationa logic d

11、ealymax =tcq+tsu+tlogic2. Please draw the RTL diagrams for the following 2 pieces VHDL codes（10 marks）（1）process(op,x,y)begin if op=0 then result = x or y; else result = x and y; end if; end process P2;（2） ENTITY test IS PORT( X,Y :in std_logic; Sum, Carry :out std_logic); END test; ARCHITECTURE dat

12、aflow OF test IS BEGIN Sum=X xor Y; Carry=X and Y; END dataflow;3. Comprehension &Design (60 marks)1、Design a 4-1Mux using synthesizable VHDL statements（10 marks） Selection signals：S0、S1;Data input：A、B、C、D；Data output： Dout 。LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;Entity Mux41 is Port(s0,s1, A,B,C,

13、D: in std_logic;Dout: out std_logic);End entity;Architecture behavior of Mux41 is Signal sel : std_logic_vector(1 downto 0); beginsel Dout Dout Dout Dout Null;end case;end process;end architecture;2、Using VHDL, describe the 2 stimuli shown by the following diagram, as a part test bench。(6 marks) Sig

14、nal S1：std_logic;Signal S2：std_logic;ProcessBeginS1=0;Wait for 10 ns;S1=1;Wait for 5 ns;S1=0;Wait for 10 ns;End process;ProcessBeginS1=0;Wait for 5 ns;S1=1;Wait for 15 ns;S1=0;Wait for 5ns;End process;3.Model the following circuit using VHDL according to the following requirements: (8 marks)(a ) TA

15、and TB are enable signals, both of them are inactive (无效), Y is set to high impedance； (b) if both of TA and TB are active(有效) , Y follows the wired-and logic (线与逻辑) of A and B； (c) if only TA （or TB） is active, Y follows input A (or input B );LIBRARY IEEE；USE IEEE.std_logic_1164.ALL;LIBRARY IEEE;US

16、E IEEE.std_logic_1164.ALL; Entity test is Port(TA,TB, A,B: in std_logic;Y: out std_logic);End entity;Architecture behavior of test is Signal sel : std_logic_vector(1 downto 0); beginsel Y Y Y Y Null;end case;end process;end architecture;4、read the following VHDL codes, and explain its function（6 mar

17、ks）Library ieee;Use ieee.std_logic_1164.all;entitys4isport( clk,rst:instd_logic;load,en:instd_logic;din:inSTD_LOGIC_VECTOR(7downto0);qb:outstd_logic);ends4;architecturebehavofs4issignalreg8 :std_logic_vector(7downto0);beginprocess(clk,RST,load,en)beginifrst=1then reg80);elsifCLKEVENTANDCLK=1then ifl

18、oad=1then reg8=din;elsifen=1then reg8(6downto0)=reg8(7downto1);endif;endifendprocessqb = _reg8(0); end behav;The vhdl codes described a right-shift register with asynchronous reset input, synchronous load input and synchronous enable signal.5、Design a up-counter based on BCD code (基于BCD码的递增计数器), whi

19、ch has the following requirements: (10 marks)(a) Load: Synchronous loading control signal;(b) Data: BCD coded data input. If Load is high, it is loaded into the counter as the initial state of counting;(c) Co: carry_out bit, if the counter value reaches 10 (decimal), the counter returns to 0 (decima

20、l), and Co is set to 1. LIBRARY IEEE;USE IEEE.std_logic_1164.ALL; Use IEEE.std_logic_unsigned.all; Entity test is Port(load,clk: in std_logic; data: in std_logic_vector(3 downto 0);Co: out std_logic);End entity;Architecture behavior of test is Signal count: std_logic_vector(3 downto 0);BeginProcess(

21、clk)beginIf clkevent and clk=1 then If load=1 thenCount=data;ElseIf count=1001 thenCount=0000;Co=1;elseCount=count+1;Co=0;End if;End if;end if;end process;end architecture;6. Solve one of the following two problems:（5 marks）（1） draw the waveforms according to the following VHDL codes. Attention: the

22、 initial value of signal a is 0, the process execution delay is assumed to be deltasignal a : std_logic:= 0; .process (a) begin a = 1; if (a = 1) then a = transport 0 after 20 ns; else a = transport 1 after 10 ns; end if; end process; （2）In a digital system, its inertial delay is assumed to be 4ns,

23、the transport delay is 3ns. The waveform of signal X is shown in the following figure，please draw the waveform of Z1, Z2.Z1= X；Z2=transport X after 3ns;7 .We have 4 pieces of VHDL codes, please choose 3 pieces, and draw their corresponding RTL diagrams. (15 marks）（a）ARCHITECTURE BEHAV OF test1 ISBEG

24、INPROCESS (clk)variable rega,regb:std_logic; BEGINif clk=1 and clkevent THEN rega:=data;regb:=rega; END IF;y=regb; END PROCESS;end behav; (b)ARCHITECTURE BEHAV OF test1 ISBEGINPROCESS (clk)variable rega,regb:std_logic; BEGINif clk=1 and clkevent THEN regb:=rega; rega:=data;END IF;y=regb; END PROCESS

25、;end behav;(c)ARCHITECTURE BEHAV OF test3 ISsignal rega,regb:std_logic; BEGINPROCESS (clk)BEGINif clk=1 and clkevent THEN regb=rega; rega=data;END IF;y=regb; END PROCESS;end behav;(d)ARCHITECTURE BEHAV OF test1 ISBEGINPROCESS (clk)variable rega: std_logic; BEGINif clk=1 and clkevent THEN rega:=data;

26、END IF;y=rega; END PROCESS;end behav;a b c d8. Using VHDL, design a circuit for counting the leading zeros of vectors. Each vector includes 8 bits, The vectors are input into the counter in serial order from LSB to MSB(由低位到高位串行输入).（1）Draw the ASM chart or the state transition diagram for the circuit

27、.（5 marks）（2）Based on the ASM chart or state transition diagram, describe the circuit using VHDL code（5 marks） LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;ENTITY leading_zeros IS PORT( clock, data,start: IN std_logic ;number : OUT std_logic_vector(3 downto 0) );END ENTITY