JESD47I中文版.docx

1、IC集成电路压力测试考核JEDEC STANDARD Stress-Test-Driven Qualification of Integrated Circuits JESD47I (Revision of JESD47H.01, April 2011) JULY 2012 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC

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7、and Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2012 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file

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9、nology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to under Standards-Documents/Copyright Information. STRESS DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS IC集成电路压力测试考核 (From JEDEC Board Ballot, JCB-12-24, formulated under the cognizance of the JC

10、14.3 Subcommittee on Silicon Devices Reliability Qualification and Monitoring.) 通过JEDEC委员会JCB-12-24号投票，在JC14.3硅晶圆器件可靠性考核和监控小组委员会审理后系统地阐述和制定1 Scope 范围 This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as produc

11、ts in a process which is being changed. 这个文档描述了用于考核新产品、同族器件或工艺变更的可接受的基准测试标准These tests are capable of stimulating and precipitating semiconductor device and packaging failures. The objective is to precipitate failures in an accelerated manner compared to use conditions. Failure Rate projections usua

12、lly require larger sample sizes than are called out in qualification testing. For guidance on projecting failure rates, refer to JESD85 Methods for Calculating Failure Rates in Units of FITs. This qualification standard is aimed at a generic qualification for a range of use conditions, but is not ap

13、plicable at extreme use conditions such as military applications, automotive under-the-hood applications, or uncontrolled avionics environments, nor does it address 2nd level reliability considerations, which are addressed in JEP150. Where specific use conditions are established, qualification testi

14、ng tailored to meet those specific requirements can be developed, using JESD94 that will result in a better optimization of resources. 这些测试用于加速和诱发半导体器件和封装的失效。目的是通过比使用环境相比加速的方式来促成失效。相比考核测试，失效率的预测需要更多的样品数量。如果需要计算预期的失效率，请参考JESD85 Methods for Calculating Failure Rates in Units of FITs。本考核标准用于制定一系列适用于一般使

15、用环境下的通用考核标准，而不是用于例如军工应用，汽车电子，或者不受控的航天电子等极端使用环境；同时本标准也不解决JEP150标准中提出的2nd等级可靠性问题。在确定具体使用条件的情况下，可以使用JESD94开发适合于满足这些特定要求的考核测试，从而更好地优化测试资源。This set of tests should not be used indiscriminately. Each qualification project should be examined for: a) Any potential new and unique failure mechanisms. b) Any s

16、ituations where these tests/conditions may induce invalid or overstress failures. 注意：不要不加选择地使用本文档中的测试。 应对每个考核项目进行确认：a）是否存在任何潜在的新的和独特的失效机制。b）任何测试或使用条件可能导致的失效或过应力失效情况。If it is known or suspected that failures either are due to new mechanisms or are uniquely induced by the severity of the test conditio

17、ns, then the application of the test condition as stated is not recommended. Alternatively, new mechanisms or uniquely problematic stress levels should be addressed by building an understanding of the mechanism and its behavior with respect to accelerated stress conditions (Ref. JESD91, “Method for

18、Developing Acceleration Models for Electronic Component Failure Mechanisms” and JESD94, “Application Specific Qualification using Knowledge Based Test Methodology”). Consideration of PC board assembly-level effects may also be necessary. For guidance on this, refer to JEP150, Stress-Test-Driven Qual

19、ification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components. This document does not relieve the supplier of the responsibility to assure that a product meets the complete set of its requirements. 如果已知或怀疑失效是由于新机制或者独特的严苛测试条件引起，则不建议使用本文档描述的测试条件。 作为一种选择，可以通过理解器件在加速

20、应力条件下的失效机制和表现，来解决新的失效机制或独特的失效问题（参考JESD91，“电子元器件失效机制加速模型的研究方法”和JESD94，“基于测试方法学的特殊考核“）。必须需要考虑PCB板级封装的影响。 有关这方面的指导，请参阅JEP150，与SMT贴装元件相关的压力测试考核和失效机制。本文件并不免除供应商确保产品符合其全部要求的责任。 2 Reference documents 参考文件 The revision of the referenced documents shall be that which is in effect on the date of the qualifica

21、tion plan. 2.1 Military 军工级 MIL-STD-883, Test Methods and Procedures for Microelectronics MIL-PRF 38535 2.2 Industrial 工业级 UL94, Tests for Flammability of Plastic Materials for Parts in Devices and Appliances. ASTM D2863, Flammability of Plastic Using the Oxygen Index Method. IEC Publication 695, Fi

22、re Hazard Testing. J-STD-020, Joint IPC/JEDEC Standard, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface-Mount Devices. JP-001, Foundry Process Qualification Guidelines (Wafer Fabrication Manufacturing Sites). JESD22 Series, Reliability Test Methods for Packaged Devices

23、 JESD46, Guidelines for User Notification of Product/process Changes by Semiconductor Suppliers. JESD69, Information Requirements for the Qualification of Silicon Devices. JESD74, Early Life Failure Rate Calculation Procedure for Electronic Components. JESD78, IC Latch-Up Test. JESD85, Methods for C

24、alculating Failure Rates in Units of FITs. JESD86, Electrical Parameters Assessment. JESD94, Application Specific Qualification using Knowledge Based Test Methodology. JESD91, Methods for Developing Acceleration Models for Electronic Component Failure Mechanisms. JEP122, Failure Mechanisms and Model

25、s for Semiconductor Devices. JEP143, Solid State Reliability Assessment Qualification Methodologies. JEP150, Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components. JESD201, Environmental Acceptance Requirements for Tin Whisker Susce

26、ptibility of Tin and Tin Alloy Surface Finishes JESD22A121, Test Method for Measuring Whisker Growth on Tin and Tin Alloy Surface Finishes 3 General requirements 通用要求 3.1 Objective 目标 The objective of this procedure is to ensure that the device to be qualified meets a generally accepted set of stres

27、s test driven qualification requirements. Qualification is aimed at components used in commercial or industrial operating environments. 本考核流程目的是确保器件能够通过一套通用的可接受的压力测试要求。主要考核目标是针对在商业或工业工作环境中使用的器件3.2 Qualification family 同族考核 While this specification may be used to qualify an individual component, it i

28、s designed to also qualify a family of similar components utilizing the same fabrication process, design rules, and similar circuits. The family qualification may also be applied to a package family where the construction is the same and only the size and number of leads differs. Interactive effects

29、 of the silicon and package shall be considered in applying family designations. 虽然本规范用于单个器件的考核，但也可用于验证使用相同晶圆制造工艺，设计规则和相似电路设计的同族器件。同时也可以用于验证结构相同但只有尺寸和管脚数量不同的封装类别。 使用同族定义时应考虑硅晶圆和封装的相互作用。3.3 Lot requirements 批次需求 Test samples shall comprise representative samples from the qualification family. Manufac

30、turing variability and its impact on reliability shall be assessed. Where applicable the test samples will be composed of approximately equal numbers from at least three (3) nonconsecutive lots. Other appropriate means may be used to evaluate manufacturing variability. Sample size and pass/fail requ

31、irements are listed in Tables 1-3. Tables A and B give guidance on translating pass/fail requirements to larger sample sizes. Generic data and larger sample sizes may be employed based upon a Chi Squared distribution using a total percent defective at a 90% confidence limit for the total required lo

32、t and sample size. ELFR requirements shall be assessed at a 60% confidence level as shown in Table B. If a single unique and expensive component is to be qualified, a reduced sample size qualification may be performed using 1/3 the sample size listed in the qualification tables. 测试样品应包含同族器件中的代表性样品，

33、需要评估生产波动性对可靠性的影响。 在适当的情况下，需要从至少三个非连续批次中抽取相同数量的样品，或者使用其他适合评估生产波动性的方法。 表1-3中列出了测试样本量和合格/不合格的要求。 表A和B给出了更大样本量情况下的合格/不合格要求。对于所有需要评估的批次和样品，可以基于卡方分布（90%可信度的总失效率），使用通用的数据和更大的样品数量。 ELFR要求按照表B所示的60可信度进行评估。如果要对一个独特且昂贵的器件进行考核评估，则可以使用考核表中列出的1/3样本量。3.4 Production requirements 产品要求 All test samples shall be fabri

34、cated and assembled in the same production site and with the same production process for which the device and qualification family will be manufactured in production. Samples need to be processed through the full production process including burn-in, handling, test, and screening. 所有测试样品需要使用相同的生产地点和

35、流程进行制造和封装，并且生产过程中需要使用相同的生产工艺。 样品需要完成整个生产流程，包括老化，搬运，测试和筛选。 3.5 Reusability of test samples测试样品的可复用性 Devices that have been used for nondestructive qualification tests may be used to populate other qualification tests. Devices that have been used in destructive qualification tests may not be used in s

36、ubsequent qualification stresses except for engineering analysis. Non-destructive qualification tests are: Early Life Failure Rate, Electrical Parameters Assessment, External Visual, System Soft Error, and Physical Dimensions. 用于非破坏性考核测试的器件可以继续用其他考核测试。 除了工程分析之外，已用于破坏性考核测试的器件不得用于随后的压力测试。 非破坏性考核测试包括：早

37、期失效率，电气参数测试，外观检查，系统软失效和物理尺寸测试。 3.6 Definition of electrical test failure after stressing 压力测试后电气失效定义 Post-stress electrical failures are defined as those devices not meeting the individual device specification or other criteria specific to the environmental stress. If the cause of failure is due to

38、causes unrelated to the test conditions, the failure shall be discounted. 压力测试后的电气失效定义是指不符合器件电气参数规范或其他环境压力测试规范。 如果失败的原因是与测试条件无关的情况造成的，则不记为失效。 3.7 Required stress tests for qualification 考核所需要的压力测试 Table 1, Table 2, and Table 3 list the qualification requirements for new components. Table 2 and Table

39、 3 are differentiated by package type, but these are not exclusively packaging tests. Interactive effects of the packaging on the silicon also drive the need for tests in Table 2 and Table 3. Power supply voltage for biased reliability stresses should be Vcc max or Vdd max as defined in the device d

40、atasheet as the maximum specified power supply operating voltage, usually the maximum power supply voltage is 5% to 10% higher than the nominal voltage. Some tests such as HTOL may allow for higher voltages to gain additional acceleration of stress time. JEP122 can provide guidance for accelerating

41、common failure mechanisms. Table 4 lists the required stresses for a qualification family or category of change. Interactive effects from the unchanged aspects of both the silicon and packaging must be assessed. 表1，表2和表3列出了新器件的考核要求。 表2和表3按封装类型区分(气密性和非气密性)，但也不只是封装的相关测试。 硅基板和封装材料的相互作用也需要参考表2和表3中的测试进行评

42、估。偏置应力可靠性测试的电源电压应该是器件数据手册中定义的最大工作电压Vcc max或Vdd max（通常最大电源电压比额定工作电压高5至10）。一些测试（如HTOL）可能允许更高的电压来获得额外的应力加速比例。 JEP122可以为加速常见失效机制提供指导。表4列出了考核 器件族或类别 变更所需的压力测试。硅晶圆和封装中都未改变部分的相互作用也必须评估。3.8 Pass/Fail criteria 合格/不合格标准 Passing all appropriate qualification tests specified in Table 1, Table 2, and Table 3, ei

43、ther by performing the test, showing equivalent data with a larger sample size, or demonstrating acceptable generic data (using an equivalent total percent defective at a 90% confidence limit for the total required lot and sample size), qualifies the device per this document. When submitting test da

44、ta from generic products or larger sample sizes to satisfy the Table 1, Table 2, and Table 3 qualification requirements of this document, the number of samples and the total number of defective devices occurring during those tests must satisfy 90% confidence level of a Poisson exponential binomial d

45、istribution, as defined in MIL-PRF 38535. MIL-PRF 38535 is available for free from /Programs/MilSpec/listdocs.asp?BasicDoc=MIL-PRF-38535. The minimum number or samples for a given defect level can be approximated by the formula: N = 0.5 2 (2C+2, 0.1) 1/LTPD 0.5 + C where C = ac

46、cept #, N=Minimum Sample Size, 2 is the Chi Squared distribution value for a 90% CL, and LTPD is the desired 90% confidence defect level. Table A is based upon this formula, but in some cases the sample sizes are slightly smaller than MIL-PRF-38535. 不管是通过执行测试，还是通过大样本量给出等效的数据，或者给出可接受的通用数据（对于所有需要评估的批次

47、和样品，使用等效的有90%置信度的总的失效百分比），来通过表1，表2和表3中指定的所有适合的考核测试。当提交来自一类产品或大样本量的测试数据来满足本文档中表1，表2和表3的考核要求时，这些测试的样本数量和出现的缺陷器件数量必须满足90%置信水平的泊松指数二项分布，详细定义参考MIL-PRF 38535。MIL-PRF 38535可以通过/Programs/MilSpec/listdocs.asp?BasicDoc=MIL-PRF-38535.免费下载。给定缺陷水平的最小数量或样本可以用下式近似： N = 0.5 2 (2C+2, 0.1) 1/LTP

48、D 0.5 + C 其中C = accept，N =最小样品数量，2是90置信度的卡方分布值，LTPD是期望的具有90置信度的缺陷级别。 表A基于此公式，但在某些情况下，样品数量略小于MIL-PRF-38535。3.8 Pass/Fail criteria (contd) 合格/失效标准表A 在90的置信度下，样本量对应的最大缺陷百分比（LTPD：Lot Tolerance Percent Defective批次缺陷百分比公差） EXAMPLE: Using generic data for HTOL with a requirement of 0 rejects from 230 sampl

49、es. If 700 samples of generic data are available, the maximum number of failures that will meet the qualification test requirement is 3 failures from the LTPD=1 column. 示例：要求测试230个样本中有失效0颗的HTOL 测试（对应的最大缺陷率是1%，置信度为90%）。 如果有700个通用数据可用，那么符合考核测试要求的最大失效数量是LTPD = 1列668对应的3颗失效。 4 Qualification and requalif

50、ication 考核和重新考核 4.1 Qualification of a new device 新器件考核 New or redesigned products (die revisions) manufactured in a currently qualified qualification family may be qualified using one (1) wafer/assembly lot. Electrical parameter assessment is one of the most important tests to run. 对于一个当前已考核的同族系列中，

51、进行新设计或重新设计的产品（芯片版本），可以只使用一个晶圆或者封装批次进行考核，电气特性是需要进行的最重要的测试之一 4.2 Requalification of a changed device 器件变更的重新考核 Requalification of a device will be required when the supplier makes a change to the product and/or process that could potentially impact the form, fit, function, quality and/or reliability o

52、f the device. The guidelines for requalification tests required are listed in Table 4. 当供应商对产品或制程进行的更改影响到了器件的外形，适配性，功能，质量或可靠性时，需要进行器件的重新考核。 表4列出了所需的重新考核试验指导。4.2.1 Process change notification PCN过程变更通知 Supplier will meet the requirements of JESD46 Guidelines for User Notification of Product/Process C

53、hanges by Semiconductor Suppliers for product/process notification changes. 对产品和过程的变更通知，供应商需要符合JESD46“半导体供应商对产品/工艺变更的用户通知指南”中的要求。4.2.2 Changes requiring requalification 变更的重新考核 All product/process changes should be evaluated against the guidelines listed in Table 4. 所有产品和工艺变更需要按照表4的指导方案进行评估4.2 Requa

54、lification of a changed device (contd) 4.2.3 Criteria for passing requalification 重新考核的通过标准 Table 4 lists qualification plan guidelines for performing the appropriate Table 1, Table 2, and Table 3 stresses. Failed devices should be analyzed for root cause and correction; only a representative sample

55、 needs to be analyzed. Acceptable resolution of root cause and successful demonstration of corrective and preventive actions will constitute successful requalification of the device(s) affected by the change. The part and/or the qualification family can be qualified as long as containment of the pro

56、blem is demonstrated until corrective and preventive actions are in place. 表4列出了执行适当的表1，表2和表3压力测试的考核计划。 对于失效器件，需要分析根本原因并纠正; 但是只需要分析其中一个代表性的样品即可。 失效根本原因的可接受的解决方案和成功预防的证明以及预防措施的实施，都可以作为受变更影响的器件重新考核说明。 只要解决和预防措施实施到位，证明该问题得到遏制，则该器件和同族器件都认为是合格的。 5 Qualification tests 考核测试 5.1 General tests 通用测试 Test deta

57、ils are given in Table 1, Table 2, and Table 3. Not all tests apply to all devices. Table 1 tests generally apply to design and fabrication process changes. Table 2 tests are for non-hermetic packaged devices, and Table 3 is for hermetic packaged devices. Table B lists the pass/fail requirements for common infant mortality levels. Table 4 gives guidance as to which tests are required for a given process change. Some of the data required may be substituted by generic process or pac