5自动化专业 单片机相关 外文文献 英文文献 外文翻译中英对照

1、西雅图视频机器人使用手册 本 科 生 毕 业 论 文（外文翻译）译文名称： mcs -51系列单片机的功能和结构 专 业： 自动化 班 次： 学 员： 指导教员： 评 阅 人： 完成时间：2010年11月30 日 海军大连舰艇学院本科生外文翻译 第14页seattle robotics cmucam1 appmod tm vision system for boebots user guidestructure and function of the mcs-51 series structure and function of the mcs-51 series one-chip compu

2、ter is a name of a piece of one-chip computer series which intel company produces. this company introduced 8 top-grade one-chip computers of mcs-51 series in 1980 after introducing 8 one-chip computers of mcs-48 series in 1976. it belong to a lot of kinds this line of one-chip computer the chips hav

3、e,such as 8051, 8031, 8751, 80c51bh, 80c31bh,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers . an one-chip computer system is made up of several following parts: ( 1) one microprocessor of 8 (cpu). ( 2

4、) at slice data memory ram (128b/256b),it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3) procedure memory rom/eprom (4kb/8kb ), is used to preserve the procedure , some initial data and form in slice. but

5、does not take rom/eprom within some one-chip computers, such as 8031 , 8032, 80c ,etc. ( 4) four 8 run side by side i/o interface p0 four p3, each mouth can use as introduction , may use as exporting too. ( 5) two timer / counter, each timer / counter may set up and count in the way, used to count t

6、o the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. ( 6) five cut off cutting off the control system of the source . ( 7) one all duplexing serial i/o mouth of uart (universal asynchronous receiver/transmitter

7、 (uart) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. ( 8) stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. allow oscillation frequency as 12 megahertas now at most. every the above-menti

8、oned part was joined through the inside data bus .among them, cpu is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc. the arithmetic unit can carry on 8 persons of arithmetic operation and unit alu o

9、f logic operation while including one, the 1 storing device temporarilies of 8, storing device 2 temporarily, 8s accumulation device acc, register b and procedure state register psw, etc. person who accumulate acc count by 2 input ends entered of checking etc. temporarily as one operation often, com

10、e from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback acc with another one. in addition, acc is often regarded as the transfer station of data transmission on 8051 inside . the same as general microprocessor, it is the busiest re

11、gister. help remembering that agreeing with a expresses in the order. the controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. the procedure counter is made up of counter of 8 for two, amounts to 16. it is a byte address cou

12、nter of the procedure in fact, the content is the next ia that will carried out in pc. the content which changes it can change the direction that the procedure carries out . shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacit

13、y, its frequency range is its 12mhz of 1.2mhz. this pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded. there

14、are rom (procedure memory , can only read ) and ram in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. procedure 8051 memory and 8751 slice procedure memory capacity 4kb, address

15、 begin from 0000h, used for preserving the procedure and form constant. data 8051- 8751 8031 of memory data memory 128b, address false 00fh, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc. in ram of this 128b, there is unit of 32 byteses tha

16、t can be appointed as the job register, this and general microprocessor is different, 8051 slice ram and job register rank one formation the same to arrange the location. it is not very the same that the memory of mcs-51 series one-chip computer and general computer disposes the way in addition. gen

17、eral computer for first address space, rom and ram can arrange in different space within the range of this address at will, namely the addresses of rom and ram, with distributing different address space in a formation. while visiting the memory, corresponding and only an address memory unit, can rom

18、, it can be ram too, and by visiting the order similarly. this kind of memory structure is called the structure of princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: the procedure stores in one and dat

19、a memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called harvard structure. but use the angle from users, 8051 memory address space is divided into three kinds: (1

20、) in the slice, arrange blocks of ffffh , 0000h of location , in unison outside the slice (use 16 addresses). (2) the data memory address space outside one of 64kb, the address is arranged from 0000h 64kb ffffh (with 16 addresses ) too to the location. (3) data memory address space of 256b (use 8 ad

21、dresses). three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: cpu visit slice, rom order spend movc , visit block ram order uses movx outside the slice, ram order uses mov to visit i

22、n slice. 8051 one-chip computer have four 8 walk abreast i/o port, call p0, p1, p2 and p3. each port is 8 accurate two-way mouths, accounts for 32 pins altogether. every one i/o line can be used as introduction and exported independently. each port includes a latch (namely special function register

23、), one exports the driver and a introduction buffer . make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of i/o in co

24、mmon use. expand among the system of memory outside having slice, p2 mouth see high 8 address off; p0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing the circuit of 8051 one-chip computers and four i/o ports is very ingenious in design. familiar with

25、 i/o port logical circuit, not only help to use ports correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. load ability and interface of port have certain requirement, because output grade, p0 of mouth and p1 end output, p3 of mo

26、uth grade different at structure, so, the load ability and interface of its door demand to have nothing in common with each other. p0 mouth is different from other mouths, its output grade draws the resistance supremly. when using it as the mouth in common use to use, output grade is it leak circuit

27、 to turn on, is it is it urge nmos draw the resistance on taking to be outer with it while inputting to go out to fail. when being used as introduction, should write 1 to a latch first. every one with p0 mouth can drive 8 model ls ttl load to export. p1 mouth is an accurate two-way mouth too, used a

28、s i/o in common use. different from p0 mouth output of circuit its, draw load resistance link with power on inside have. in fact, the resistance is that two effects are in charge of fet and together: one fet is in charge of load, its resistance is regular. another one can is it lead to work with clo

29、se at two state, make its president resistance value change approximate 0 or group value heavy two situation very. when it is 0 that the resistance is approximate , can draw the pin to the high level fast ; when resistance value is very large, p1 mouth, in order to hinder the introduction state high

30、. output as p1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw the resistance on neednt answer and thenning. here when the port is used as introduction, must write into 1 to the corresponding latch first too, make fet end. relatively about 20,00

31、0 ohms because of the load resistance in scene and because 40,000 ohms, will not exert an influence on the data that are input. the structure of p2 some mouth is similar to p0 mouth, there are mux switches. is it similar to mouth partly to urge, but mouth large a conversion controls some than p1. p3

32、 mouth one multi-functional port, mouth getting many than p1 it have and 3 door and 4 buffer. two part these, make her besides accurate two-way function with p1 mouth just, can also use the second function of every pin, and door 3 function one switch in fact, it determines to be to output data of la

33、tch to output second signal of function. act as w =at 1 oclock, output q end signal; act as q =at 1 oclock, can output w line signal . at the time of programming, it is that the first function is still the second function but neednt have software that set up p3 mouth in advance . it hardware not ins

34、ide is the automatic to have two function outputted when cpu carries on sfr and seeks the location (the location or the byte ) to visit to p3 mouth /at not lasting lining, there are inside hardware latch qs =1.the operation principle of p3 mouth is similar to p1 mouth. output grade , p3 of mouth , p

35、1 of p1 , connect with inside have load resistance of drawing , every one of they can drive 4 model ls ttl load to output. as while inputting the mouth, any ttl or nmos circuit can drive p1 of 8051 one-chip computers as p3 mouth in a normal way . because draw resistance on output grade of them have,

36、 can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outerly . mouths are all accurate two-way mouths too. when the conduct is input, must write the corresponding port latch with 1 first . as to 80c51 one-chip computer, port

37、 can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base , in order to the electricity while restraining the high level from exporting p1p3 being restored

38、to the throne is the operation of initializing of an one-chip computer. its main function is to turn pc into 0000h initially , make the one-chip computer begin to hold the conduct procedure from unit 0000h. except that the ones that enter the system are initialized normally,as because procedure oper

39、ate it make mistakes or operate there arent mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. it is an input end which is restored to the throne the signal in 8051 china rst pin. restore to the throne signal high level e

40、ffective , should sustain 24 shake cycle (namely 2 machine cycles ) the above its effective times. if 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. produce the logic picture of circuit

41、 which is restored to the throne the signal:restore to the throne the circuit and include two parts outside in the chip entirely. outside that circuit produce to restore to the throne signal (rst ) hand over to schmitts trigger, restore to the throne circuit sample to output , schmitt of trigger con

42、stantly in each s5p2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal insidly. restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signa

43、l high level duration greater than 2 machine cycles to guarantee. being restored to the throne in the circuit is simple, its function is very important. pieces of one-chip computer system could normal running,should first check it can restore to the throne not succeeding. checking and can pop ones h

44、ead and monitor the pin with the oscillograph tentatively, push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.mcs -51系列单片机

45、的功能和结构 mcs - 51系列单片机具有一个单芯片电脑的结构和功能，它是英特尔公司生产的系列产品的名称。这家公司在1976年推出后，引进8位单芯片的mcs - 48系列计算机后于1980年推出的8位的mcs - 51系列单芯片计算机。诸如此类的单芯片电脑有很多种，如8051，8031，8751，80c51bh，80c31bh等，其基本组成，基本性能和指令系统都是相同的。 8051是51系列单芯片电脑的代表。 一个单芯片的计算机系统由以下几个部分组成：（1）一个8位的微处理器（cpu）。（2）片内数据存储器ram（128b/256b），它只读/写数据，如结果不在操作过程中，最终结果要显示数据

46、（3）程序存储器rom/ eprom（4kb/8kb），是用来保存程序，一些初步的数据和切片的形式。但一些单芯片电脑没有考虑rom / eprom，如8031，8032，80c51等等。（4）4个8路运行的i / o接口，p0，p1,p2,p3，每口可以用作入口，也可以用作出口。 （5）两个定时/计数器，每个定时/计数器可设置和计数的方式，用来计数外部事件，可以设置成定时方式也可以根据计算结果或定时控制实现计算机。 （6）5个中断 （7）一个全双工串行的i / uart（通用异步接收器i口/发送器（uart），它是实现单芯片电脑或单芯片计算机和计算机的串行通信使用。 （8）振荡器和时钟产生电路

47、，需要考虑石英晶体微调能力。允许振荡频率为12mhz，每一个上述的部分都是通过内部数据总线连接。其中cpu是一个芯片计算机的核心，它是计算机的指挥中心，是由算术单元和控制器等部分组成。算术单元可以进行8位算术运算和逻辑运算， alu单元是其中一种运算器，1 8个存储设备，暂存设备的积累设备进行协调，程序状态寄存器psw积累了2个输入端的计数等检查暂时作为一个操作往往由人来操作谁储存1输入的是它使操作去上暂时计数，另有一个操作的结果，回环协调。此外，协调往往是作为对8051内的数据传输转运站考虑。作为一般的微处理器，它是最繁忙的，帮助记住和同意与其的顺序表示。该控制器包括程序计数器，解密的顺序。

48、振荡器和定时电路等的程序计数器是一个由8个计数器为2，总计 16位。这是一个字节的地址，其实程序计数器，是将在个人电脑内进行。从而改变它的内容可以改变方向的程序进行。在8051的单芯片电脑中的电路，只需要外部石英晶体和频率微调电容，其频率范围为1.2mhz的其12mhz的。这种脉冲信号，作为8051的工作，即单位时间的最低基本节奏。 8051是其他电脑一样，在拍控制的基本工作在和谐，就像一个管弦乐队，根据击败发挥是指挥。 有光盘（程序存储器，只能读取），并在8051片（数据存储器ram，可以是可写可读，他们各自独立的内存地址空间，处理办法是，与一般的电脑记忆体相同。 8051和8751的程序存

49、储器的存储容量4kb的程序切片，地址开始从0000h开始执行，维护的程序和形式不断使用。数据8051 - 8751的内存数据存储器128b条8031，地址虚假00fh，中层结果存入操作使用，数据存储和数据是暂时缓冲等。在这128b条内存，有32 字节，可以作为工作寄存器使用，这和一般的微处理器是不同的，8051片ram和登记形成的同一级到安排的位置。这不是很相同的，mcs - 51系列内存的单芯片计算机和通用计算机作主除了道路。通用计算机的第一个地址空间，rom和ram，可安排在不同的空间在这个范围内的地址范围，即rom和ram地址的形成与分布在不同的地址空间。在访问内存，相应的，只有一个地址

50、的内存单元，可以用外部存储，也可以内存，并通过访问顺序与此类似。这种内存结构的一种被称为普林斯顿结构。 8051记忆分为程序存储器空间和数据存储空间的物理结构上划分，有四个在所有的记忆体空间：在1和数据外部数据存储器和程序存储器空间之一，一组在外面一个内存空间的程序商店，结构这一种形式的程序和数据存储器器件数据存储器分开的形式，称为哈佛结构。但是，从用户使用，8051的内存地址空间分为三种：分为（1）片内，（使用16个地址一致的ffffh，地点为0000h，块）。 （2）64kb的外部数据存储器空间的一个地址，该地址是从0000h开始执行64kb的ffffh安排16地址，也到该位置。 （3）数

51、据存储器的256b（使用8个地址）的地址空间。上述三个内存空间的地址重叠，区分和设计的8051指令系统中不同的数据传输顺序代码：cpu的访问片，访问ram块顺序使用movx指令外片，内存为访问片。 8051单芯片的电脑有4个8步行并进的i / o端口，分别为p0，p1，p2和p3。每个端口8位的双向口，共占了32针。每一个i / o线可作为独立的入口和出口。每个端口包括一个锁存器（即特殊功能寄存器），1名入口和1出口引进缓冲区。使数据能锁存输出时，数据缓冲区时，可以引进，但4个通道这些自我相同的功能。系统中的内存片展开外来的，这四个港口可作为准确的双向的i /共同使用输出口。系统的内存中展开外

52、来的片，p2口处于高位，8地址关闭;入口p0口是双向总线，发送地址和8个低数据。 8051单芯片电脑的4个i / o端口是非常巧妙的电路设计。熟悉i/ o端口的逻辑电路，不仅有助于正确和合理利用端口，并在一定程度上将有助于设计周边的单芯片计算机的逻辑电路。在一定程度上负载能力和端口界面有一定的要求，因为输出级，和p1口输出端，p3口与p0口结构的不同，因此，负载能力和接口需求互相无太多共同之处。求解p0口是与其他口不同，它的输出级提请阻力。当使用的常用是它的输出级电路泄漏打开，它是利用它敦促采取nmos管能与它外部的阻力，而输入走出失败。当被用作数据，应该写“1”到内部，每一个p0口与一个可以

53、驱动8型号ls ttl负载出口。p1口是一个准确的双向口，共同使用输出口。不同在p0口输出的电路，得出与负载功率电阻内有联系。事实上，阻力是，两个效果是在场效应管，共同负责：一个场效应管的负载负责，它的电阻是正常的。另一条是它可以导致在两个工作状态密切，使其电阻值变化近似0或2组值的情况非常严重。当它是0，该阻力是近似的，可以提请较快的高层次，当电阻值是非常大的，p1口以阻碍引进高电平。为p1口输出高电平时，它是可以借鉴的负载提供电流向外，提请电阻无须回答。在这里，当端口作为引进使用，必须首先写入1到相应的锁存，使fet的结束。相对约20,000欧姆，因为在现场，因为负载电阻和40,000欧姆，不会产生对输入的数据的影响。一些为p2结构类似于p0口，有mux的开关。它是类似口部分，大的一个转换控制p1口的多功能端口，获得第一位，这有很多“与”门和4个缓冲。两部分，其中除了作出准确的双向功能，还可以使用第二个函数的每一个针“与”门三功能开关，实际上，它决定将输出数据锁存到输出的函数的第二个信号为w = 1点，输出q端信号。法令;法为q = 1时时，可以输出w线路信号，在制定方案的时侯，那就是第一个函数仍是第二个功能，但不必软件预先设置p3口。it硬件里面是不是有自动两个函数输出时的cpu进行sfr和要求的位置（位置或字节）来访问，在没有至p3口，里面有硬件锁q报表，p3口