数字电路英文版-第七单元

1、数字电路英文版数字电路英文版-第七单元第七单元 ABEL ( 件描述语言的一种件描述语言的一种) Architecture ( 结构体结构体 )Array ( 阵列阵列 ) Buffer ( 缓冲器缓冲器 )Cell ( 单元单元 ) Compiler ( 编辑器编辑器 )Documentation file ( 使用说明文件使用说明文件 ) Fuse ( 熔丝熔丝 )E2CMOS ( 电可擦除的电可擦除的CMOS ) GAL ( 通用阵列逻辑器件通用阵列逻辑器件 )Input file ( 输入文件输入文件 ) Input/Output ( I/O ) ( 输入输入/输出输出 )JEDEC

2、file ( 标准数据格式文件标准数据格式文件 ) OLMC (输出逻辑宏单元输出逻辑宏单元 )PAL ( 可编程阵列逻辑可编程阵列逻辑 ) PLA ( 可编程逻辑阵列可编程逻辑阵列)PLD ( 可编程逻辑器件可编程逻辑器件 ) Programmer ( 编程器编程器 )PROM ( 可编程只读存储器可编程只读存储器 ) Software ( 软件软件 )Synthesis ( 综合综合 ) Tristate output buffer ( 三态输出缓冲器三态输出缓冲器 )ZIF socked ( 不用力插座不用力插座 ) KEY TERMSABEL Advanced Bollean Expr

3、ession Language. A software compiler language for PLD programming; a type of hardware description language (HDL).Architecture The internal functional arrangement of the elements that give a device its particular operating characteristics.Array In a PLD, a matrix formed by rows of product-term lines

4、and columns of input lines with a programmable cell at each junction.Buffer A circuit that prevents loading of an input or output.Cell A fused cross point of a row and columnn in a PLD.Complier Software that translates from high-level language that uses words or symbols, such as HDL , into low-level

5、 machine language (1s and 0s).Documentation file The information from a computer that documents the final design after the input been processed.E2CMOS Electrically earsable CMOS ( EECMOS). The circuit technology used for the reprogrammable cells in GAL.Fuse The programmable element in certain types

6、of PLDs; also called a fusible link.GAL Generic array logic. A PLD with a reprogrammable AND array, a fixed OR array, and programmable output logic macrocells.Input file The information entered in a computer that describes logic design using a PLD programming language such as HDL.Input/Output (I/O)

7、A terminal of a device that can be used as either an input or as an output.OLMC Output logic marcocell. The programmable output logic in a GAL.PAL Programmable array logic. A PLD with a programmable AND array and a fixed OR array.PLA Programmable logic array. A PLD with a programmable AND and OR arr

8、ay.PLD Programmable logic device.Programmer An instrument that programs PLD using a JEDEC from a computer running HDL software.Software Computer programs; programs that instruct a computer what to do in order to carry out a given set of tasks.Synthesis The software process of converting a circuit de

9、scription to a standard JEDEC PLD programming.Tristate output buffer A logic circuit having three output states: HIGH, LOW, and high impedance (open).数字电路英文版数字电路英文版-第七单元第七单元 ZIF socket Zero insertion force socket. A type of socket used in most programmers that accepts a PLD package.Programmable logi

10、c devices (PLDs) are used in many applications to replace SSI and MSI circuits; they save space and reduce the actual number and cost of devices in a given design. 2A PLD consist of a large array of AND gates and OR gates that can be programmed to achieve specified logic functions. Four types of dev

11、ices that are classified as PLDs are the programmable read-only memory (PROM), the programmable logic array (PLA), the programmable array logic (PAL), and the generic array logic (GAL).3数字电路英文版数字电路英文版-第七单元第七单元 Programmable ArraysThe OR ArrayAABBX1X2X3Fusible link4AABBX1 =A+BX2 =A+BX3 =A+B5数字电路英文版数字电

12、路英文版-第七单元第七单元 The AND ArrayAABBX1X2X36AABBX1=ABX2=ABX3=AB7Classification of PLDsProgrammable Read-Only MemoryFixedAND arrayProgrammableOR arrayOutput 1Input 1Input 2Input nOutput 2Output m8Programmable Logic Array (PLA)ProgrammableAND arrayProgrammableOR arrayOutput 1Input 1Input 2Input nOutput 2Out

13、put m9Programmable Array Logic (PAL)ProgrammableAND arrayFixed OR array andoutput logicOutput 1Input 1Input 2Input nOutput 2Output m10Generic Logic Array (GAL)ProgrammableAND arrayFixed OR array andProgrammableoutput logicOutput 1Input 1Input 2Input nOutput 2Output m11The PAL and the GAL are the mos

14、t common PLDs used for logic implementation. As you learned in the last section, the PAL in its basic form is a PLD with a one-time programmable AND array and fixed OR array. In this section, you will learn how PALs are used to produce specified combinational logic functions and examine a specific P

15、AL.12PAL Operation ( SOP )AABBX13Implementing a Sum-of-Products Expression X = AB +AB +ABAABBX14Simplified SymbolsAABBXAB4ABABAB15XXXXXXProgrammable Array Logic (PAL)ProgrammableAND arrayFixed OR arrayOutput 1Input 1Input 2Input nOutput 2Input 3Output mOutputlogicOutputlogicOutputlogic16PAL Output C

16、ombination LogicOutputFrom ANDGate arrayTristate control(a) Combination output (active-LOW).17I/OFrom ANDGate arrayTristate control(b) Combination input/output (active-LOW).18数字电路英文版数字电路英文版-第七单元第七单元 I/OFrom ANDGate arrayTristate control(c) Programmable polarity outputProgrammable fuse19数字电路英文版数字电路英文

17、版-第七单元第七单元 Standard PAL NumberingPAL 10L8Programmable array logicTen inputsEight outputsActive-LOW output20The GAL in its basic form is a PLD with a reprogrammable AND array, a fixed OR array, and programmable output logic. In this section, basic concepts are introduced and Section 7-4 and 7-5 speci

18、fic GALs are examined.GAL Operation electrically erasable CMOS (E2CMOS)21AABBXE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOS22AABBOffOnOffOffOffOffOffOffOffOffOffOffOffOffOffOffOffOffOffOnOnOnOnOnABABAB

19、 X=AB+AB+AB23数字电路英文版数字电路英文版-第七单元第七单元 The GAL Block DiagramE2CMOSProgrammableAND arrayI/O 1Input 1Input 2Input nI/O 2Input 3I/O mOLMCOLMCOLMC24数字电路英文版数字电路英文版-第七单元第七单元 Standard GAL NumberingGAL 16V8Generic array logicSixteen inputsEight outputsVariable-output configuration25The various GALs all have t

20、he same type of programmable array. The differ in the size of the array, in the type of OLMCs , and in operating parameters such as speed and power dissipation. In this section, a popular generic array logic device, the GAL22V10, is discussed.26Logic Diagram1-of-4multiplexer1-of-2multiplexerFlip-Flo

21、pOLMCS1S0S1I/O27The Output Logic Macrocells (OLMCs)As stated in the discussion of GALs , an OLMC contains programmable logic circuits that can be either for a combinational output or input or for a registered output.281-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1S0S1I/O(a) Active-LOW output S1=1

22、, S0=0291-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1S0S1I/O(b) Active-HIGH output S1=1, S0=130InputOutputTristate controlHIGHLOWHIGHActive stateLOW(a)HIGHLOWHIGHActive stateHigh-impedance state(b)31Output or Input Selection1-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1S0S1HIGHOutput(a) Outpu

23、t321-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1S0S1LOWInput(b) Input331-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1=1S0=1S1=1HIGHX=ABCD+ ABCD+ ABCD+ ABCD+ ABCD+XABCDABCDABCDABCDABCDABCDABCDActive HIGHRelated Problem Write the SOP expression for the output if S0=0, S1= 1( Active LOW )1-of-4m

24、ultiplexer1-of-2multiplexerFlip-FlopOLMCS1=1S0=0S1=1HIGHX=ABCD+ ABCD+ ABCD+ ABCD+ ABCD+ABCDXABCDABCDABCDABCDABCDABCD( Active LOW )Example 7-6 Show how the following 6-variable SOP function is implemented with the AL22V10X=ABCDEF+ ABCDEF+ ABCDEF+ ABCDEF+ ABCDEF+ABCDEF+ ABCDEF0 3 4 7B BC CD DE EF F8 1

25、1 12 15 16 19 20 2340 43A1OHIGHS0=1S1=1OLMCAs you have learned, PLAs are programmed by leaving specified fusible links intact and blowing open all others. GALs are programmed in a similar way except the E2CMOS cells are turned on or off. The logic functions to be implemented determines which cells a

26、re affected. 34数字电路英文版数字电路英文版-第七单元第七单元 In order to program a PLA or GAL, the following items are required: a computer, programming software, and a PLD programmer.Computer: Any computer that meets the software and programmer specifications can be used.35Software: The software packages for PLD program

27、ming are called logic compliers. The Programmer: The programmer has a software driver program that reads JEDEC file generated by the logic complier and converts it to instructions for applying required voltages to specified PLD pins to alter the specified cells in the array as directed by the fuse m

28、ap.36STARTDesign thelogic circuitEnter designinto computerSyntax orOther errors?ComplierDesignsimulationDesignflaw?processes inputminimizes logicDebugEditYesNoNoYes37数字电路英文版数字电路英文版-第七单元第七单元 Complier createsJEDEC file (fuse map)Download toprogrammerProgrammer “burns”fuse map into PLDarrayComplier gen

29、erates documentation file38The Programming ProcessEntering the Design: The logic design is entered into the computer by creating an input or source file. Running the Software: The software complier processes and translates the input minimizes the logic.39数字电路英文版数字电路英文版-第七单元第七单元 Programming the Devic

30、e: When the design is finalized, the compiler creates a fuse map (JEDEC file) and downloads it to the programmer. 40数字电路英文版数字电路英文版-第七单元第七单元 As mentioned earlier, there are several software packages for implementing logic designs in PLDs. ABEL is commonly used hardware description languages (HDLs).41

31、数字电路英文版数字电路英文版-第七单元第七单元 Introduction to ABEL: ABEL, which is the acronym for Advanced Boolean Expression Language, allows logic designs to be implemented in programmable in programmable logic devices.42数字电路英文版数字电路英文版-第七单元第七单元 Logic Design Entry : ABEL provides three different formats for describing

32、and entering a logic design from the from the computer keyboard: equations, truth tables, and state diagrams.43数字电路英文版数字电路英文版-第七单元第七单元 Design Simulation : Once a logic circuit design has been entered, its operation can be simulated using test vectors to make sure there are no design errors.44数字电路英文版

33、数字电路英文版-第七单元第七单元 Logic Synthesis : The software process of converting a circuit description in the form of equations, truth tables, or state diagrams to a standard JEDEC required to actually implement the design in a PLD is called logic synthesis .45数字电路英文版数字电路英文版-第七单元第七单元 Boolean Operations:Logic O

34、peration ABEL Symbol NOT ! AND & OR # XOR $46数字电路英文版数字电路英文版-第七单元第七单元 Standard Boolean ABEL A !A AB A & B A + B A # B +A B A $ B47EXAMPLE 7-7 Write each of the following logic expressions in ABEL: X= ABC +ABC +AB + BC Y= ( A + B + C + D )( A + B + C )Solution X = A&!B&C#!A!B!C#A&B#!B&C Y =(!A#B#!C#D)&(A#B#C)RP: W= X+Y,Where X=ABC, Y=A+B+C48数字电路英文版数字电路英文版-第七单元第七单元 EXAMPLE 7-8MultiplexerA3A2A1A0B3B2B1B0Y3Y2Y1Y0C3C2C1C0S1S049数字电路英文版数字电路英文版-第七单元第七单元 Select Input Data Output S1 S0 Y3 Y2 Y1 Y0 0 1 A3 A2 A1 A0 1 0 B3 B2 B1 B0 1 1 C3 C2