单片机 外文翻译 外文文献 英文文献 SPCE061A 32K x 16 语音控制器

1、spce061a 32k x 16 sound controller1. general descriptionthe spce061a, a 16-bit architecture product, carries the newest 16-bit microprocessor, nsp (pronounced as micro-n-sp), developed by sunplus technology. this high processing speed assures the nsp is capable of handling complex digital signal pro

2、cesses easily and rapidly. therefore, the spce061a is applicable to the areas of digital sound process and voice recognition. the operating voltage of 3.0v through 3.6v and speed of 0.32mhz through 49.152mhz yield the spce061a to be easily used in varieties of applications. the memory capacity inclu

3、des 32k-word flash memory plus a 2k-word working sram. other features include 32 programmable multi-functional i/os, two 16-bit timers/counters, 32768hz real time clock, low voltage reset/detection, eight channels 10-bit adc (one channel built-in mic amplifier with auto gain controller), 10-bit dac

4、output and many others.block diagram3. features 16-bit nsp microprocessor cpu clock: 0.32mhz - 49.152mhz operating voltage: 3.0v - 3.6v program flash operating voltage: 3.0v - 3.6v io porta & b operating voltage: 3.0v - 5.5v 32k-word flash memory 2k-word working sram software-based audio processing

5、crystal resonator standby mode (clock stop mode) for power savings, max. 2.0a vdd = 3.6v two 16-bit timers/counters two 10-bit dac outputs 32 general i/os (bit programmable) 14 int sources with two priority levels key wakeup function (ioa0 - 7) approx. 190 sec speech 2.0kbit/per sec with sacm_s200 p

6、ll feature for system clock 32768hz real time clock (rtc) eight channels 10-bit ad converter adc external top reference voltage 2.0v voltage regulator output, 5ma of driving capability serial interface i/o (sio) built-in microphone amplifier and agc function uart receiver and transmitter (full duple

7、x) low voltage reset and low voltage detection watchdog enable (bonding option) ice function for development and down load into flash memory security function to protect code to be read and written.4. application field voice recognition products intelligent interactive talking toys advanced educatio

8、nal toys kids learning products kids storybook general speech synthesizer long duration audio products recording / playback productssignal descriptions5. functional descriptions5.1. cputhe spce061a is equipped with a 16-bit nsp, the newest 16-bit microprocessor by sunplus and pronounced as micro-n-s

9、p. eight registers are involved in nsp: r1 - r4 (general-purpose registers), pc (program counter), sp (stack pointer), base pointer (bp) and sr (segment register). the interrupts include three fiqs (fast interrupt request) and eight irqs (interrupt request), plus one software-interrupt, break.moreov

10、er, a high performance hardware multiplier with the capability of fir filter is also built in to reduce the software multiplication loading.5.2. memory5.2.1. sramthe amount of sram is 2k-word (including stack), ranged from $0000 through $07ff with access speed of two cpu clock cycles.5.2.2. flash me

11、moryflash memory ($008000 $00ffff) is a high-speed memory with access speed of two cpu clock cycles. flash erase and program functions must be used in ide tools.5.3. pll, clock, power mode5.3.1. pll (phase lock loop)the purpose of pll is to provide a base frequency (32768hz) and to pump the frequenc

12、y from 20.48mhz to 49.152mhz for system clock (fosc). the default pll frequency is 24.576mhz.5.3.1.1. system clockbasically, the system clock is provided by pll and programmed by the port_systemclock (w) to determine the frequency of clock for system. the default system clock fosc = 24.576mhz and cp

13、u clock is fosc/8 if not specified. the initial cpu clock is fosc/8 after system wakes up and to be adjusted to desired cpu clock by programming the port_systemclock (w). this avoids flash rom reading failure when system wakes up.5.3.1.2. 32768hz rtcthe real time clock (rtc) is normally used in watc

14、h, clock or other time related products. a 2hz-rtc (1/2 second) function is loaded in spce061a. the rtc counts the timing as well as to wake cpu up whenever rtc occurs. since the rtc is generated each 0.5 seconds, time can be traced by the numbers of rtc occurrence. in addition, spce061a supports 32

15、768hz oscillator in normal mode and auto-power-saving mode. in normal mode, 32768hz osc always runs at the highest power consumption. in auto-power-saving mode, however, it runs in normal mode for the first 7.5 seconds and changes back to power-saving mode automatically to save powers.5.4. standby m

16、odethe spce061a also offers a standby mode for low power application needs. to enter standby mode, the desired key wakeup port (ioa 7:0) must be configured to input first. and read the port_ioa_latch(r) to latch the ioa state before entering the standby mode. also remember to enable the correspondin

17、g interrupt source(s) for wakeup. after that, stop the cpu clock by writing the stop clock register (b0b2 of port_systemclock (w) to enter standby mode. in such mode, sram and i/os remain in the previous states till cpu being awoken. the wakeup sources in spce061a include port ioa7 - 0 and irq1 - ir

18、q6. after spce061a is awoken, the cpu will continue to execute the program. programmer can also enable or disable the 32768hz osc when cpu is in standby mode.5.5. low voltage detection and low voltage reset 5.5.1. low voltage detection (lvd) there are two lvd levels to be selected: 2.9v, and 3.3v. t

19、hese levels can be programmed via port_lvd_ctrl (w). as an example, suppose lvd is given to 2.9v. when the voltage drops below 2.9v, the b15 of port_lvd_ctrl is read as high. in such state, program can be designed to react to this condition. 5.5.2. low voltage reset in addition to the lvd, the spce0

20、61a has another important function, low voltage reset (lvr). with the lvr function, a reset signal is generated to reset system when the operating voltage drops below 2.3v for 10 consecutive cpu clock cycles. without lvr, the cpu becomes unstable and malfunctions when the operating voltage drops bel

21、ow 2.3v. the lvr will reset all functions to the initial operational (stable) states when the voltage drops below 2.3v. a lvr timing diagram is given as follows: 5.6. interruptthe spce061a has 14 interrupt sources, grouped into two types, fiq (fast interrupt request) and irq (interrupt request). the

22、 priority of fiq is higher than irq. fiq is the high-priority interrupt while irq is the low-priority one. an irq can be interrupted by a fiq, but not by another irq. a fiq cannot be interrupted by any other interrupt sources.5.7. i/otwo i/o ports are built in spce061a, porta and portb. the porta is

23、 an ordinary i/o with programmable wakeup capability. in addition to the regular io function, the portb can also perform some special functions in certain pins. suppose operating voltage is running at 3.6v (vdd) and vddio (power for i/o) operates from 3.6v (vdd) to 5.5v. in such condition, the i/o p

24、ad is capable of operating from 0v through vddio. however iob13 and iob14 are recommended to operate =3.6v during standby mode, otherwise these two ios will have current leakage. the following diagram is an i/o schematic.although data can be written into the same register through port_data and port_

25、buffer, they can be read from different places, buffer (r) and data (r). the ioa 7:0 is the key wakeup port. to activate key wakeup function, latch data on port_ioa_latch and enable the key wakeup function. wakeup is triggered when the porta state is different from at the time latched. in addition t

26、o an ordinary i/o port, portb carries some special functions. a summary of portb special functions is listed as follows: refer to the above table, the configuration of iob2, iob3, iob4, and iob5 involves feedback function in which an osc frequency can be obtained from ext1 (ext2) by simply adding a

27、rc circuit between iob2 (iob3) and iob4 (iob5).5.8. timer / counterthe spce061a provides two 16-bit timers/counters, timera and timerb. the timera is called a universal counter. timerb is a general-purpose counter. the clock source of timera comes from the combination of clock source a and clock sou

28、rce b. in timerb, the clock source is given from source c. when timer overflows, an int signal is sent to cpu to generate a time-out signal.initially, write a value of n into a timer and select a desired clock source, timer will start counting from n, n+1, n+2, . through ffff. an int (timera/timerb)

29、 signal is generated at the next clock after reaching “ffff” and the int signal is transmitted to int controller for further processing. at the same time, n will be reloaded into timer and start all over again. the clock source a is a high frequency source and clock source b is a low frequency sourc

30、e. the combination of clock source a and b provides a variety of speeds to timera. a “1” represents pass signal and not gating. in contrast, “0” indicates deactivating timer. the ext1 and ext2 are the external clock sources. moreover, counter can generate time-out signal for input clock source to a

31、four bits (16 levels) pwm pulse width counter. a variety of clock duration can be generated and exported from iob8 (apwmo) and iob9 (bpwmo).the following example is a 3/16-duration cycle. the apwmo waveform is made by selecting a pulse width through port_timera_ctrl (w) 9:6. as a result, each 16 cyc

32、les will generate a pulse width defined in control port. these pwm signals can be applied for controlling the speed of motor or other devices.generally speaking, the clock source a and c are fast clock sources and source b comes from rtc system (32768hz). therefore, clock source b can be utilized as

33、 a precise counter for time counting, e.g., the 2hz clock can be used for real time counting.5.8.1. timebasetimebase, generated by 32768hz, is a combination of frequency selections. the outputs of timebase block are named to tmb1 and tmb2. tmb1 is frequency for timera (clock source b). the tmb1 and

34、tmb2 are the sources for interrupt (irq6). furthermore, timebases generates additional 2hz to 4096hz interrupt sources (irq4 and irq5) for real-time-clock (rtc).5.9. sleep, wakeup and watchdog5.9.1. wakeup and sleep1) sleep: after power-on reset, ic starts running until a sleep command occurs. when

35、a sleep command is accepted, ic will turn the system clock (pll) off. after all, it enters sleep mode.2) wakeup: cpu waking up from sleep mode requires a wakeup signal to turn the system clock (pll) on. the irq signal makes cpu to complete the wakeup process and initialization. the key wakeup and in

36、terrupt sources (irq1 - irq6) can be used for wakeup sources.5.9.2. watchdogthe purpose of watchdog is to monitor if the system operates normally. within a certain period, watchdog must be cleared. if watchdog is not cleared, cpu assumes the program has been running in an abnormal condition. as a re

37、sult, the cpu will reset the system to the initial state and start running the program all over again. the watchdog function can be removed by bonding option. in spce061a, the clear period is 0.75 seconds. if watchdog is cleared within each 0.75 seconds, the system will not be reset. to clear watchd

38、og, simply write “xxxx xxxx xxxx xx01b” to port_watchdog_clear(w). the content written to port_watchdog_clear(w) for watchdog clearance must be exactly the same as the one illustrated above (xxxx xxxx xxxx xx01b). other values given to the port_watchdog_clear(w) for watchdog clearance may end up wit

39、h system reset. the watchdog function remains enabled during standby mode if the 32768hz is turned on.5.10. adc (analog to digital converter) / dacthe spce061a has eight channels 10-bit adc (analog to digital converter). the function of an adc is to convert analog signal to digital signal, e.g. a vo

40、ltage level into a digital word. the eight channels of adc can be seven channels of line-in from ioa 6:0 or one channel microphone (mic) input through amplifier and agc controller. the mic amplifier circuit is capable of reducing common mode noise by transmitting signals through differential mic inp

41、uts (micn, micp). moreover, an external resistor can be applied to adjust microphone gain and time of agc operating. the ad needs to select source of line-in before conversion. the adc is able to choose the external or internal (=avdd) top reference voltage. if constant voltage source is unavailable

42、, spce061a offers a constant voltage 2.0v with 5.0ma driving ability with a capacitor connected.the spce061a has two 10-bit d/a with 2.0ma or 3.0ma driving current for audio outputs, dac1 and dac2.5.11. serial interface i/o (sio)serial interface i/o offers a one-bit serial interface for communicatio

43、n. this serial interface is capable of transmitting or receiving data via two i/o pins, iob0 (sck) and iob1 (sda).5.12. uartuart block provides a full-duplex standard interface that facilitates the communication with other devices. with this interface, spce can transmit and receive simultaneously. t

44、he maximum baud-rate can be up to 115200bps. this function can be accomplished by using portb and interrupt (uart irq). the rx and tx of uart are shared with iob7 and iob10. when spce061a receives and/or transmits a frame of data, the b7 (rxrdy) and/or b6 (txrdy) in port_uart_command2(r) will be set

45、 to “1” and the uart irq is activated at the same time.spce061a 32k x 16 语音控制器1. 总述spce061a 是继nsp系列产品spce500a等之后凌阳科技推出的又一个16位结构的微控制器。与spce500a不同的是，在存储器资源方面考虑到用户的较少资源的需求以及便于程序调试等功能，spce061a里只内嵌32k字的闪存flash rom。较高的处理速度使nsp能够非常容易地、快速地处理复杂的数字信号。因此，与spce500a相同，以nsp为核心的spce061a微控制器也适用在数字语音识别应用领域。spce061a在

46、2.6v3.6v电压范围内的工作速度范围为0.32mhz49.152mhz，较高的工作速度使其应用领域更加拓宽。2k字sram和32k字闪存rom仅占一页存储空间，32位可编程的多功能i/o端口；两个16位定时器/计数器；32768hz实时时钟；低电压复位/监测功能；8通道10位模-数转换输入功能并具有内置自动增益控制功能的麦克风输入方式；双通道10位dac方式的音频输出功能。spce061a是数字声音和语音识别产品的一种最经济的应用。2. 性能 16位nsp微处理器； 工作电压：vdd为2.63.6v(cpu), vddh为vdd5.5v(i/o)； cpu时钟：0.32mhz49.152m

47、hz ； 内置2k字sram； 内置32k闪存rom； 可编程音频处理； 晶体振荡器； 系统处于备用状态下(时钟处于停止状态)，耗电小于2a3.6v； 2个16位可编程定时器/计数器(可自动预置初始计数值)； 2个10位dac(数-模转换)输出通道； 32位通用可编程输入/输出端口； 14个中断源可来自定时器a / b，时基，2个外部时钟源输入，键唤醒； 具备触键唤醒的功能； 使用凌阳音频编码sacm_s240方式(2.4k位/秒)，能容纳210秒的语音数据； 锁相环pll振荡器提供系统时钟信号； 32768hz实时时钟； 7通道10位电压模-数转换器(adc)和单通道声音模-数转换器 声音模

48、-数转换器输入通道内置麦克风放大器和自动增益控制(agc)功能； 具备串行设备接口； 低电压复位(lvr)功能和低电压监测(lvd)功能； 内置在线仿真板(ice，in- circuit emulator)接口。3. 结构框图spce061a的结构如下图3.1所示：图3.14. 应用领域 语音识别类产品 智能语音交互式玩具 高级亦教亦乐类玩具 儿童电子故事书类产品 通用语音合成器类产品 需较长语音持续时间类产品5. 功能描述5.1. cpuspce061a配备了凌阳科技开发的最新的16位微处理器nsp。它内含有8个寄存器：4个通用寄存器r1r4，1个程序计数器pc，1个堆栈指针sp，1个基址指

49、针bp和1个段寄存器sr。通用寄存器r3和r4结合形成一个32位寄存器mr，mr可被用作乘法运算和内积运算的目标寄存器。此外，spce061a有3个fiq中断和14个irq中断，并且带有一个由指令break控制的软中断。nsp不仅可以进行加、减等基本算术运算和逻辑运算，还可以完成用于数字信号处理的乘法运算和内积运算。5.2. 存储器5.2.1. ramspce061a拥有2k字的sram(包括堆栈区)，其地址范围从$000000到$0007ff。5.2.2. 闪存（flash）rom全部32k字闪存均可在ice工作方式下被编程写入或被擦除。对闪存设置保密设定后，其内容将不能再通过ice被读写，

50、也就可以使程序不被其他人读取。5.3. 时钟（锁相环振荡器，系统时钟，实时时钟）5.3.1. 锁相环(pll，phase lock loop)振荡器pll的作用是为系统提供一个实时时钟的基频(32768hz)，然后将基频进行倍频，调整至49.152mhz、40.96mhz、32.768mhz、24.576mhz或20.480mhz。系统默认的pll自激振荡频率为24.576mhz。pll的结构如下图5.1所示：图5.15.3.2. 时钟5.3.2.1. 系统时钟系统时钟的信号源为pll振荡器。系统时钟频率(fosc)和cpu时钟频率(cpuclk)可通过对p_systemclock(写)($7

51、013h)单元编程来控制。默认的fosc、cpuclk分别为24.576mhz和fosc/8。用户可以通过对p_systemclock单元编程完成对系统时钟和cpu时钟频率的定义。当系统被唤醒后最初时刻的cpuclk频率亦为fosc/8，随后逐渐被调整到用户设定的cpuclk频率。这样，可避免系统在唤醒初始时刻读rom出现错误。5.3.2.2. 实时时钟（32768hz）32768hz实时时钟通常用于钟表、实时时钟延时以及其它与时间相关类产品。spce061a通过对32768hz实时时钟源分频而提供了多种实时时钟中断源。例如，用作唤醒源的中断源irq5_2hz，表示系统每隔0.5秒被唤醒一次，

52、由此可作为精确的计时基准。”除此之外，spce061a 还支持rtc振荡器强振模式/自动模式的转换。处于强振模式时，rtc振荡器始终运行在高耗能的状态下。处于自动弱振模式时，系统在上电复位后的前7.5s内处于强振模式，然后自动切换到弱振模式以降低功耗。下图5.2为spce061a与晶体振荡器的连接电路原理图。图5.25.4. 节电模式spce061a可设置节电的备用模式以达到节能的目的。在这种工作模式下，只需很小（小于2a）的备用电流。要进入待命工作模式，首先应将所需的键唤醒口ioa70设为输入端口。在进入待命工作模式前，通过读p_ioa_latch单元来激活ioa70口的唤醒功能，或者允许作

53、为唤醒源的中断源中断请求的响应；然后通过写入p_systemclock单元一个cpuclk stop控制字（cpu睡眠信号），以停止cpuclk工作，进入睡眠状态。p_systemclock单元还可用来编程设置在cpu进入睡眠时是禁止/允许32768hz实时时钟的工作。在待命模式下，ram和i/o端口的状态都将维持进入睡眠前的各个状态，直到产生唤醒信号。spce061a的唤醒源包括键唤醒ioa70端口以及各中断源（irq0 irq6）。当spce061a的cpu被唤醒后，会继续执行程序指令。5.5. 低电压监测和低电压复位5.5.1. 低电压监测 (lvd，low voltage detect

54、)低电压监测功能可以提供系统内电源电压的使用情况。4级电压监测低限：2.4v、2.8v、3.2和3.6v，可通过对p_lvd_ctrl单元编程进行控制。假定vlvd=3.2v，当系统电压vcc低于3.2v时，p_lvd_ctrl单元的第15位返回值为“1”，这样，cpu可以通过可编程电压监测低限来完成低电压监测。系统默认的电压监测低限为2.4v。5.5.2. 低电压复位 (lvr，low voltage reset)引起spce061a复位通常有2个途径：电源上电复位、低电压复位（lvr）。当电源电压低于2.2v时，系统会变得不稳定且易出故障。导致电源电压过低的原因很多，如电压的反跳、负载过重

55、、电池能量不足。如果系统设置了低电压复位(lvr)功能，当电源电压低于该值时，会在4个时钟周期之后产生一个复位信号，使系统复位。如下图5.3：图5.35.6. 中断（interrupt）spce061a具有两种中断方式：快速中断请求fiq(fast interrupt request)中断和中断请求irq(interrupt request)中断。中断控制器可处理3种fiq中断和14种irq中断，以及一个由指令break控制的软中断。相比之下，fiq中断的优先级较高而irq中断的优先级较低。也就是说，fiq中断可以中断irq中断服务子程序的执行，而cpu执行相应的fiq中断服务子程序的过程不能

56、被任何中断源的中断请求中断。下表1列出了中断的优先级别：表15.7. 输入/输出端口（i/o，input/output）输入输出端口是系统与其它设备进行数据交换的接口。spce061a具有两个可编程输入输出端口：a口和b口。a口既是具有可编程唤醒功能的普通i/o口，又可与adc的多路line_in输入共用(ioa60与line_in17共用；b口除了具有普通i/o口的功能外，在特定的管脚上还可以完成一些特殊的功能。i/o端口如下图5.4所示：图5.4尽管数据能通过数据端口p_iox_data和数据缓冲器端口p_iox_buffer写入相同的数据寄存器，但从这两个端口读出的数据却来自不同的位置；

57、从后者读出的仍是数据寄存器里的数据，而从前者读出的是i/o管脚上的电平状态。ioa70口为键唤醒源，通过读p_ioa_latch单元来锁存ioa70端口的电平状态，从而可激活其唤醒功能。当ioa70口的状态和锁存时的状态不一致时，会触发系统由节电的睡眠工作模式切换到唤醒模式。b口除了具有常规的输入/输出端口功能外，还有一些特殊的功能，如下表2所示：表2如下图5.5所示的电路显示了带有反馈应用的iob2、iob3、iob4和iob5等端口的设置情况。有了反馈功能，只要在iob2(iob3)和iob4(iob5)之间增加一个rc电路就可以从ext1 (ext2)得到振荡源频率信号。图5.55.8. 定时器/计数器（timer/counter）spce061a提供了两个16位的定时器/计数器：timera和timerb。timera为通用计数器；timerb为多功能计数器。timera的时钟源由时钟源a和时钟源b进行“与”操作而形成；timerb的时钟源仅为时钟源a。定时器发生溢出后会产生一个溢出信号(taout/tbout)。一方面，它会作为定时器中断信号传输给cpu中断系统；另一方面，它又会作为4位计数器计数的时钟源信号，输出一个具有4位可调的脉宽调制占空比输出信号apwmo或bpwmo(分别从iob8 和i