干凯磊_实现R型指令的CPU设计实验

1、实验报告姓名干凯磊学号12051709班级计科4班专业计算机科学与应用课程名称计算机组成原理课程设计任课老师赵辽英指导老师赵辽英实验名称实现R型指令的CPU设计实验实验时间5月26日1 实验目的(1) 掌握MIPS R型指令的数据通路设计，掌握指令流和数据流的控制方法；(2) 掌握完整的单周期CPU顶层模块的设计方法；(3) 实现MIPS R型指令的功能；二实验内容 MIPS R型指令格式及编码字段OPrsrtrdshamtfunc功能描述位数655556汇编助记符 编码add rd，rs,rt000000rsrtrd00000100000算数加：rs+rtrdsub rd ,rs,rt000

2、000rsrtrd00000100010算数减:rs-rtrdand rd,rs,rt000000rsrtrd00000100100逻辑与:rs&rtrdor rd,rs,rt000000rsrtrd00000100101逻辑或:rs|rtrdxor rd,rs,rt000000rsrtrd00000100110逻辑异或：rsrtrdnor rd,rs,rt000000rsrtrd00000100111逻辑或非：(rs|rt)rdsltu rd,rs,rt000000rsrtrd00000101011无符号数小于则置位：if(rsrt)rd=1 else rd=0sllv rd,rt,rs00

3、0000rsrtrd00000000100逻辑左移：(rtrs)rd三实验代码module R_CPU(rst,clk,SW,LED,ALU_F);input rst,clk;input 1:0 SW;output reg 7:0 LED;output 31:0 ALU_F;wire 31:0 Inst_code;R_CPU_1 my_cpu(clk,rst,ALU_F);always(*)begincase(SW1:0)2b00: LED7:0=ALU_F7:0;2b01: LED7:0=ALU_F15:8;2b10: LED7:0=ALU_F23:16;2b11: LED7:0=ALU_F

4、31:24;default: LED7:0=8b00000000;endcaseendendmodulemodule R_CPU_1(input clk,input rst,output 31:0 ALU_F);wire 31:0 Inst_code;wire 4:0 Rs,Rt,Rd;wire 5:0 OP,func;wire 31:0 ALU_A,ALU_B;wire ZF,OF;reg Write_Reg;reg Set_ZF,Set_OF;reg 2:0 ALU_OP;IF my_if(.clk(clk),.rst(rst),.Instr_Code(Inst_code);assign

5、OP = Inst_code31:26;assign Rs = Inst_code25:21;assign Rt = Inst_code20:16;assign Rd = Inst_code15:11;assign func = Inst_code5:0;REG my_reg(.Clk(clk),.Reset(rst),.R_Addr_A(Rs),.R_Addr_B(Rt),.W_Addr(Rd),.W_Data(ALU_F),.Write_Reg(Write_Reg),.R_Data_A(ALU_A),.R_Data_B(ALU_B);ALU my_alu(.F(ALU_F),.ZF(ZF)

6、,.OF(OF),.A(ALU_A),.B(ALU_B),.ALU_OP(ALU_OP);always(*)beginALU_OP = 3b000;Write_Reg = 1b0;Set_ZF = 1b0;Set_OF = 1b0;if (OP=6b000000) beginWrite_Reg = 1b1; Set_ZF = 1b1; case (func) 6b100000:ALU_OP=100;6b100010:ALU_OP=101;6b100100:ALU_OP=000;6b100101:ALU_OP=001;6b100110:begin ALU_OP=010;Set_OF=1; end

7、6b100111:begin ALU_OP=011;Set_OF=1; end6b101011:ALU_OP=110;6b000100:ALU_OP=111;endcaseendendendmodulemodule IF(input rst,input clk,output 31:0 Instr_Code);wire 31:0 pc_new;reg 31:0 pc;ROM your_instance(.clka(clk),.addra(pc7:2),.douta(Instr_Code); assign pc_new=pc+4;always(negedge clk or posedge rst)

8、beginif(rst)pc=32h00000000;elsepc=pc_new;endendmodulemodule REG( input Clk, input Reset, input 4:0 R_Addr_A, input 4:0 R_Addr_B, input 4:0 W_Addr, input 31:0 W_Data, input Write_Reg, output 31:0 R_Data_A, output 31:0 R_Data_B );reg 31:0 REG_Files0:31;integer i;assign R_Data_A = REG_FilesR_Addr_A;ass

9、ign R_Data_B = REG_FilesR_Addr_B;always (posedge Clk or posedge Reset)beginif(Reset)beginfor(i=0;i=31;i=i+1)REG_Filesi= 32h0000_0000;endelsebeginif (Write_Reg) REG_FilesW_Addr B)?Zero_32:One_32; SRL: F=BA; endcase end assign ZF = |F;assign SF=F31;assign PF=F;endmodule四电路图5 引脚配置六实验结果及分析 R型指令CPU实验结果记录表序号指令执行结果结论10000ffff00000000正确20025ffffffffffff正确30125ffff00000001正确40175ffff00000002正确50225ffff00000004正确60275ffff00000005正确70325ffffffffffe0正确80375fffffffffffe正确90425fff