简易数字频率计

1、简易数字频率计实验要求设计一个四位数字频率计，此频率计共分四档。一档：09999hz二档：1099.99khz三档：100999.9 khz四档：1999mhz1. 分频器模块原理图如下：源程序如下library ieee;use ieee.std_logic_1164.all;entity fen is port(clk:in std_logic; q:out std_logic);end fen;architecture behav of fen isbegin process(clk) variable clkk1:std_logic:=0; begin if clk event and

2、 clk=1then clkk1:= not clkk1; end if; q=clkk1; end process;end behav;仿真波形2. 测频模块ftest原理图如下：源程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ftest is port(clr,fx,door:in std_logic; alm:out std_logic; q3,q2,q1,q0,dang:out std_logic_vector(3 downto 0);end ftest;archite

3、cture corn_arc of ftest isbegin process(door,fx) variable c0,c1,c2,c3,c4,c5,c6:std_logic_vector(3 downto 0); variable x:std_logic; begin if fxevent and fx=1then if door=1then if c01001then c0:=c0+1; else c0:=0000; if c11001then c1:=c1+1; else c1:=0000; if c21001then c2:=c2+1; else c2:=0000; if c3100

4、1then c3:=c3+1; else c3:=0000; if c41001then c4:=c4+1; else c4:=0000; if c51001then c5:=c5+1; else c5:=0000; if c61001then c6:=c6+1; else c6:=0000; alm=1; end if; end if; end if; end if; end if; end if; end if; else if clr=0then alm=0; end if; c6:=0000; c5:=0000; c4:=0000; c3:=0000; c2:=0000; c1:=00

5、00; c0:=0000; end if; if c6/=0000then q3=c6; q2=c5; q1=c4; q0=c3; dang=0100; elsif c5/=0000then q3=c5; q2=c4; q1=c3; q0=c2; dang=0011; elsif c4/=0000then q3=c4; q2=c3; q1=c2; q0=c1; dang=0010; else q3=c3; q2=c2; q1=c1; q0=c0; dang=0001; end if; end if; end process; end corn_arc;仿真波形3. lock模块源程序libra

6、ry ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity lock is port(a4,a3,a2,a1,a0:std_logic_vector(3 downto 0); clk:in std_logic; q4,q3,q2,q1,q0:out std_logic_vector(3 downto 0);end lock;architecture one of lock isbegin process(clk) variable t4,t3,t2,t1,t0:std_logic_vector(3 downto 0); begin if(clkevent and clk=0)then t4:=a4; t3:=a3; t2:=a2; t1:=a