数字电路设计课件第10讲数字电路中的时序问题

1、ee141 digital integrated circuits2ndtiming issues1ee141 digital integrated circuits2ndtiming issues2combina t io n allogicr1r2cincoutoutinclkee141 digital integrated circuits2ndtiming issues3ee141 digital integrated circuits2ndtiming issues4dclkqdqclktc-qtholdpwmtsutd-qdelays can be different for ri

2、sing and falling data transitionstee141 digital integrated circuits2ndtiming issues5dclkqdqclktc-qtholdttsudelays can be different for rising and falling data transitionsee141 digital integrated circuits2ndtiming issues6ee141 digital integrated circuits2ndtiming issues7ee141 digital integrated circu

3、its2ndtiming issues8243power s u p p l yinterco n n e c t5 tempera t u r e6 capacit iv e loa d7 couplin g t o ad jacen t lines1 clock g e n e r ati ondevicessources of clock uncertaintyee141 digital integrated circuits2ndtiming issues9r1in(a) pos it i v e s kewcombina t io n allogicdqtclk1clkdelaytc

4、lk2r2dqcombina t io n allogictclk3r3 dqdelayr1in(b) neg a t i v e s kewcombina t io n allogicdqtclk1delaytclk2r2dqcombina t io n allogictclk3r3 dqdelayclkee141 digital integrated circuits2ndtiming issues10clk1clk2tclkdtclk+d+ thd2143launching edge arrives before the receiving edgeee141 digital integ

5、rated circuits2ndtiming issues11clk1clk2tclkdtclk +d2143receiving edge arrives before the launching edge竞争现象永远不可能出现竞争现象永远不可能出现但是影响电路性能但是影响电路性能ee141 digital integrated circuits2ndtiming issues12regregreg.reglogoutinclock distributionpositive skewnegative skewdata and clock routing设计一个偏差小的时钟网络是非常重要的设计

6、一个偏差小的时钟网络是非常重要的！ee141 digital integrated circuits2ndtiming issues13ee141 digital integrated circuits2ndtiming issues14q时钟抖动是指在芯片上的某一个给定点上时钟周时钟抖动是指在芯片上的某一个给定点上时钟周期发生暂时性的变化，即时钟周期在每个不同的期发生暂时性的变化，即时钟周期在每个不同的周期上可以缩短或加长。周期上可以缩短或加长。q时钟抖动是严格衡量时钟暂时不确定性的一项指时钟抖动是严格衡量时钟暂时不确定性的一项指标，并且经常针对某一给定点进行说明。标，并且经常针对某一给定点

7、进行说明。q抖动可以使用许多方法来衡量和表征，它是一个抖动可以使用许多方法来衡量和表征，它是一个平均值为零的随机变量平均值为零的随机变量ee141 digital integrated circuits2ndtiming issues15clk-tjittertclktjitterclk incombinationallogic tc-q , tc-q, cdtlogictlogic, cdtsu, tholdregstjitter最坏情况下，周期至周期抖动绝对值等最坏情况下，周期至周期抖动绝对值等于绝对抖动的于绝对抖动的2 2倍倍（2tjitter）ee141 digital integra

8、ted circuits2ndtiming issues16时钟抖动直接降低了一个时序电路的性能。时钟抖动直接降低了一个时序电路的性能。如果性能是一个电路的关键因素，应该严格如果性能是一个电路的关键因素，应该严格把抖动限定在一定的范围内。把抖动限定在一定的范围内。ee141 digital integrated circuits2ndtiming issues17ee141 digital integrated circuits2ndtiming issues18clock skew 0clock skew 0时的维持时间约束条件：时的维持时间约束条件：clock skew0clock ske

9、w0时的约束条件：时的约束条件：ee141 digital integrated circuits2ndtiming issues19时序分析结果与前面分析的情况一致时序分析结果与前面分析的情况一致负偏差会降低性能负偏差会降低性能ee141 digital integrated circuits2ndtiming issues20clkclock is distributed in a tree-like fashionh-treeee141 digital integrated circuits2ndtiming issues21restle98ee141 digital integrate

10、d circuits2ndtiming issues22driverdriverdriverdrivergclkgclkgclkgclkno rc-matchinglarge poweree141 digital integrated circuits2ndtiming issues23clock frequency: 300 mhz - 9.3 million transistorstotal clock load: 3.75 nfpower in clock distribution network : 20 w (out of 50)uses two level clock distri

11、bution: single 6-stage driver at center of chip secondary buffers drive left and right sideclock grid in metal3 and metal4total driver size: 58 cm!ee141 digital integrated circuits2ndtiming issues24q2 phase single wire clock, distributed globallyq2 distributed driver channels reduced rc delay/skew i

12、mproved thermal distribution 3.75nf clock load 58 cm final driver widthqlocal inverters for latchingqconditional clocks in caches to reduce powerqmore complex race checkingqdevice variationtrise = 0.35ns tskew = 150pstcycle= 3.3nsclock waveformlocation of clockdriver on diepre-driverfinal driversee1

13、41 digital integrated circuits2ndtiming issues25clock driversee141 digital integrated circuits2ndtiming issues26ee141 digital integrated circuits2ndtiming issues27q2 phase, with multiple conditional buffered clocks2.8 nf clock load40 cm final driver widthqlocal clocks can be gated “off” to save powe

14、rqreduced load/skewqreduced thermal issuesqmultiple clocks complicate race checkingtrise = 0.35nstskew = 50pstcycle= 1.67nsglobal clock waveformpllee141 digital integrated circuits2ndtiming issues28ee141 digital integrated circuits2ndtiming issues29gclk skew(at vdd/2 crossings)ps5101520253035404550e

15、e141 digital integrated circuits2ndtiming issues30ee141 digital integrated circuits2ndtiming issues31q为使偏差最小，可以采用为使偏差最小，可以采用h h树或者更为一般的布树或者更为一般的布线匹配的树结构，使从中央时钟分配源到单个钟线匹配的树结构，使从中央时钟分配源到单个钟控元件的时钟路径均衡。在采用时钟树布线时，控元件的时钟路径均衡。在采用时钟树布线时，必须使包括导线和晶体管负载在内的每条路径时必须使包括导线和晶体管负载在内的每条路径时钟负载相等。钟负载相等。q采用局部时钟网络（而不是树型布线

16、）可以减小采用局部时钟网络（而不是树型布线）可以减小时钟偏斜，但代价是增加了电容负载和功耗时钟偏斜，但代价是增加了电容负载和功耗。ee141 digital integrated circuits2ndtiming issues32q如果与数据相关的时钟负载变化引起了如果与数据相关的时钟负载变化引起了显著的抖动，就应当使用时钟负载不受显著的抖动，就应当使用时钟负载不受数据影响的差分寄存器。数据影响的差分寄存器。q数据如果沿一个方向流动，可以使数据数据如果沿一个方向流动，可以使数据和时钟按相反方向布线。这样可以消除和时钟按相反方向布线。这样可以消除竞争，代价是性能有所降低竞争，代价是性能有所降低

17、. .ee141 digital integrated circuits2ndtiming issues33q通过将时钟线与相邻信号线屏蔽，可以避免与通过将时钟线与相邻信号线屏蔽，可以避免与数据相关的噪声。把电源线（数据相关的噪声。把电源线（vddvdd或或gndgnd）放在）放在时钟线的旁边可以减少或避免与相邻信号网络时钟线的旁边可以减少或避免与相邻信号网络的耦合。的耦合。q由于层间绝缘电介质厚度不均造成互连电容的由于层间绝缘电介质厚度不均造成互连电容的变化可以通过采用虚设填料来大大减少。虚设变化可以通过采用虚设填料来大大减少。虚设填料的是使用非常普遍，它通过提高绝缘层的填料的是使用非常普遍

18、，它通过提高绝缘层的一致性来减少时钟偏差。系统性的偏差应通过一致性来减少时钟偏差。系统性的偏差应通过模拟并予以弥补模拟并予以弥补。ee141 digital integrated circuits2ndtiming issues34q芯片上各处温度不均匀会引起时钟缓冲延时的芯片上各处温度不均匀会引起时钟缓冲延时的变化，采用基于延时锁定环（变化，采用基于延时锁定环（delay-locked loop)delay-locked loop)的的反馈电路可以弥补温度偏差问题。反馈电路可以弥补温度偏差问题。q电源供电不稳是引起抖动的重要原因，因为这电源供电不稳是引起抖动的重要原因，因为这会使经过时钟缓冲器的延时在周期与周期之间会使经过时钟缓冲器的延时在周期与周期之间不同。通过加入片上去耦电容可以