VHDL第一次实验报告要点

1、深圳大学实验报告课程名称：EDA技术实验项目名称:基本电路行为的描述学院：信息工程学院专业：电子信息工程指导教师:报告人;_学号;班级： 2实验时间：实验报告提交时间： 2014年5月9日教务部制实验内容：1多路选择器（习题2.1 ）2 ROM （习题 3.4）3简易加法器（习题3.5）4通用译码器（习题4.4）5 第五章习题 5.1、5.5、5.6、5.7、5.8实验要求:1 .依次完成各电路功能的VHDL弋码编写2 .完成相应电路仿真，并对仿真结果截图，截图中要求尽可能多的体现不同 输入信号对应的输入结果3 .完成实验报告，并按时提交至 Blackboard ,实验报告见实验报告模板，要

2、求按模板各项内容完成。4 .特别提示：实验报告按模板内容逐项填写，要求有完整的VHDL弋码、仿真测试文件（VHDLtest bench）、仿真结果截图、仿真结果分析、实验结论（或 对实验的总结、心得体会）等内容。实验过程及内容:2.1多路选择器多路选择器的顶层电路如图 P2.1所示。根据真值表，如果输入 sel= "01” 或者sel= "10”，那么输出将等于对应的某一输入（c=a或c=b）.然而如果 输入sel= "00”或者sel= "11”，那么输出将分别为0和'Z'（高阻）。selc000110110 a b Z(a)填写表格，

3、完成下面的代码。(b)是对你的解答给出相关的注释。将代码编译后进行仿真，验证其正确性。实验完整VHDL弋码：library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity mux isPort ( a : in STD_LOGIC_VECTOR(7 DOWNTO 0); b : in STD_LOGIC_VECTOR(7 DOWNTO 0); sel : in STD_LOGIC_VECTOR(1 DOWNTO 0); c : out STD_LOGIC_VECTOR(7 DOWNTO 0); end mux;architecture example of mu

4、x isbeginPROCESS (a,b,sel)beginIF (sel="00") THENc <= "00000000"ELSIF (sel="01") THENc <= a;ELSIF (sel="10") THENc <= b;ELSEc <= (OTHERS => 'U');END IF;END PROCESS;end EXAMPLE;仿真测试文件代码：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY Test

5、_Mux ISEND Test_Mux;ARCHITECTURE behavior OF Test_Mux ISCOMPONENT muxPORT(a : IN std_logic_vector(7 downto 0);b : IN std_logic_vector(7 downto 0);sel : IN std_logic_vector(1 downto 0);c : OUT std_logic_vector(7 downto 0);END COMPONENT;-Inputssignal a : std_logic_vector(7 downto 0) := (others => &

6、#39;0');signal b : std_logic_vector(7 downto 0) := (others => '0');signal sel : std_logic_vector(1 downto 0) := (others => '0');-Outputssignal c : std_logic_vector(7 downto 0);-No clocks detected in port list. Replace <clock> below with-appropriate port nameBEGIN-Inst

7、antiate the Unit Under Test (UUT) uut: mux PORT MAP (a => a, b => b, sel => sel, c => c);-Stimulus process stim_proc: process begin-hold reset state for 100 ns. a<="10101010”;b<="11110000”;sel <="00"wait for 100 ns;sel <="01"wait for 100 ns;sel &

8、lt;="10"wait for 100 ns;sel <="11"wait for 100 ns;-insert stimulus herewait;end process;END;仿真结果：1D101Q1DILllDOaD it11: 4C3.415 怔vaImJLIUULIUUT!01llllMOaVSPX-KU * 1口1 口 曰:.I一门1门7WO E!e|I I I I I I I LLoiqioio- LllOCiOOtilO SE11cnnnniuu如图，当输入信号sel为“00”时，输出信号c为“00000000'；当输入

9、信号sel为“01”时，输出信号c等于a即为“10101010”；当输入信号sel为“10” 时，输出信号c等于b即为“11110000'当输入信号sel为其他情况时，输 出信号c等于自己设定的值，在此处即为“ U'。习题3.4 ROM试用1*1维常数来实现只读存储器 ROM( read-only memory ),假设一个ROM 由许多深度为8,位宽为4的块组成。提示：首先建立一个名为rom的数组， 然后定义一个rom类型的信号来实现ROM用常数值填充到ROW中： CONSTANT my_rom:rom:=(values);。实验完整VHDL弋码：library IEEE;u

10、se IEEE.STD_LOGIC_1164.ALL;entity ROM isPort ( addr : in integer range 0 to 7;data : out STD_LOGIC_vector(3 downto 0); end ROM;architecture Behavioral of ROM isTYPE ROM IS ARRAY (0 TO 7) OF STD_LOGIC_VECTOR(3 DOWNTO 0);CONSTANT my_rom:ROM:= ("0000", "0001","0010", "

11、;0011", "0100", "0101", "0110", "0111");begindata <=my_rom(addr);end Behavioral;仿真测试文件代码：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY rom1 IS END rom1;ARCHITECTURE behavior OF rom1 IS-Component Declaration for the Unit Under Test (UUT)COMPONENT ROMP

12、ORT(addr : IN integer range 0 to 7 ;data : OUT std_logic_vector(3 downto 0)；END COMPONENT;-Inputssignal addr : integer range 0 to 7;-Outputssignal data : std_logic_vector(3 downto 0);-No clocks detected in port list. Replace <clock> below with-appropriate port nameBEGIN-Instantiate the Unit Un

13、der Test (UUT) uut: ROM PORT MAP (addr => addr, data => data);-Stimulus processstim_proc: process begin-hold reset state for 100 ns.addr<=0;wait for 100 ns;addr<=2;wait for 100 ns;addr<=3;wait for 100 ns;addr<=5;wait for 100 ns;addr<=7;wait for 100 ns;addr<=1;wait for 100 ns;

14、wait;end process;END;仿真结果:如图。当输入信号addr为“0”时，输出信号data为“0000”；当输入信号 addr为“2”时，输出信号data为“0010”；当输入信号addr为“3”时， 输出信号data为“0011”；当输入信号addr为“5”时，输出信号data为“0101”； 当输入信号addr为“7”时，输出信号data为“0111”；当输入信号addr 为“1”时，输出信号data为“0001”。习题3.5简易加法器重新编写一段代码，实现例3.3所示的加法器，要求所有输入/输出信号的类 型均为STD_LOGIC_VECTOR示：回顾3.8节所学的内容)。实

15、验完整VHDL弋码：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_arith.all;use IEEE.STD_LOGIC_unsigned.all;entity adder1 isPort ( a : in STD_LOGIC_VECTOR (3 DOWNTO 0);b : in STD_LOGIC_VECTOR (3 DOWNTO 0);sum : out STD_LOGIC_VECTOR (4 DOWNTO 0);end adder1;architecture Behavioral of adder1 isbegi

16、nsum <= ('0'&a)+('0'&b);end Behavioral;仿真测试文件代码：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY adder2 ISEND adder2;ARCHITECTURE behavior OF adder2 IS-Component Declaration for the Unit Under Test (UUT)COMPONENT adder1PORT(a : IN std_logic_vector(3 downto 0);b : IN std_log

17、ic_vector(3 downto 0);sum : OUT std_logic_vector(4 downto 0);END COMPONENT;-Inputssignal a : std_logic_vector(3 downto 0) := (others => '0');signal b : std_logic_vector(3 downto 0) := (others => '0');-Outputssignal sum : std_logic_vector(4 downto 0);-No clocks detected in port

18、list. Replace <clock> below with-appropriate port nameBEGIN-Instantiate the Unit Under Test (UUT) uut: adder1 PORT MAP (a => a, b => b, sum => sum);-Stimulus process stim proc: processbegin-hold reset state for 100 ns.a <="0000" b <="0001"wait for 100 ns;a &l

19、t;="0010" b <="0011"wait for 100 ns;a <="0100" b <="0101"wait for 100 ns;a <="0110" b <="0111"wait for 100 ns;a <="1000" b <="1001"wait for 100 ns;a <="1010" b <="1011"wait

20、for 100 ns;a <="1100" b <="1101"wait for 100 ns;a <="1110" b <="1111"wait for 100 ns;wait;end process;END;如图。当输入信号a为“0000”，b为“0001”时，输出信号sum为“00001”; 当输入信号a为“0010”，b为“0011”时，输出信号sum为“00101”；当输 入信号a为“0100”，b为“0101”时，输出信号sum为“01001”；当输入信 号a为“0110”，b为

21、“0111”时，输出信号sum为“01101”；当输入信号a 为“1000”，b为“1001”时，输出信号sum为“10001”；当输入信号a为“1010”, b为“1011”时，输出信号sum为“10101”；当输入信号a为“1100”，b为“1101”时，输出信号sum为“11001”；当输入信号a为“1110”，b为“1111” 时，输出信号sum为“11101”。习题4.4通用译码器下面这个习题和例4.1中的译码器电路有关。(1)在例4.1给出的电路中，如果矢量的位宽发生变化，那么程序中的信号 sel(第7行)和(第8行)的位宽也要相应的改变。如果想要把例4.1中的设 计修改为一个通用

22、译码器。为此必须在ENTITY中使用GENERI码句指定sel 的位宽(假设n=3),然后用n的函数来替代sel和x的位宽上界。综合后， 对电路进行仿真，验证其正确性。实验完整VHDL弋码：library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity decoded isGENERIC (n: INTEGER :=3);Port ( ena : in STD_LOGIC;sel : in STD_LOGIC_VECTOR(n-1 DOWNTO 0);x : out STD_LOGIC_VECTOR(2*n)-1 DOWNTO 0); end decoder1;

23、architecture Behavioral of decoder1 isbeginPROCESS (ena, sel)VARIABLE temp1: STD_LOGIC_VECTOR(x'HIGH DOWNTO 0);VARIABLE temp2: INTEGER RANGE 0 TO x'HIGH; BEGINtemp1 := (OTHERS => '1');temp2 := 0;IF (ena= '1') THENFOR i IN sel'RANGE LOOPIF (sel(i) ='1') THENtemp

24、2 :=2*temp2+1;ELSEtemp2 :=2*temp2;END IF;END LOOP;temp1(temp2) :='0'END IF;x <= temp1;END PROCESS;END Behavioral;仿真测试文件代码：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY decoder2 ISEND decoder2;ARCHITECTURE behavior OF decoder2 ISCOMPONENT decodedPort ( ena : in STD_LOGIC;sel : in STD_LOG

25、IC_VECTOR(2 DOWNTO 0);x : out STD_LOGIC_VECTOR(7 DOWNTO 0);END COMPONENT;-Inputssignal ena : std_logic := '0'signal sel : std_logic_vector(2 downto 0) := (others => '0');-Outputssignal x : std_logic_vector(7 downto 0);-No clocks detected in port list. Replace <clock> below w

26、ith-appropriate port nameBEGIN-Instantiate the Unit Under Test (UUT)uut: decoder1 PORT MAP ( ena => ena, sel => sel, x => x);-Stimulus processstim_proc: process begin-hold reset state for 100 ns.ena<='1' sel<="010"wait for 100 ns;ena<='1' sel<="100

27、"wait for 100 ns;ena<='1' sel<="110"wait for 100 ns;ena<='1' sel<="100" wait for 100 ns;ena<='1' sel<="101"wait for 100 ns;ena<='1' sel<="111"wait for 100 ns;ena<='1' sel<="101&quo

28、t; wait for 100 ns;-insert stimulus herewait;end process;END;仿真结果:如图。让使能端始终为“ 1”。当输入信号sel为“010”时，输出信号x为 “11111011”；当输入信号sel为“100”时，输出信号x为“11101111”；当输入信号sel为“110”时，输出信号x为“10111111”；当输入信号sel为 “100”时，输出信号x为“11101111”；当输入信号sel为“101”时，输出 信号x为“11011111”；当输入信号sel为“111”时，输出信号x为“01111111”； 当输入信号sel为“101”时，输

29、出信号x为“11011111”。(2)在例4.1的设计中引入了一个二进制整数到整数的转换函数(第 20行 第26行)。如果把sel声明为整数，就不需要使用这个转换函数。要求读者 修改代码，将信号sel声明为整数类型。当信号sel的位宽用n来指定时， 代码才是通用的。综合代码并进行仿真。实验完整VHDL弋码：library IEEE;use IEEE.STD LOGIC 1164.ALL;entity decoder3 isGENERIC (n: INTEGER :=3);Port ( ena : in STD_LOGIC;sel : in INTEGER RANGE 0 TO (2*n)-1;

30、x : out STD_LOGIC_VECTOR(2*n)-1 DOWNTO 0);end decoder3;architecture Behavioral of decoder3 is beginPROCESS (ena, sel)VARIABLE temp1: STD_LOGIC_VECTOR(x'HIGH DOWNTO 0); BEGINtemp1 := (OTHERS => '1');IF (ena= '1') THEN temp1(sel) :='0'END IF;x <= temp1;END PROCESS;END

31、 Behavioral;仿真测试文件代码：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY decorder4 ISEND decorder4;ARCHITECTURE behavior OF decorder4 IS-Component Declaration for the Unit Under Test (UUT)COMPONENT decoder3PORT(ena : IN std_logic;sel : IN integer range 0 to 7;x : OUT std_logic_vector(7 downto 0) );END C

32、OMPONENT;-Inputssignal ena : std_logic := '0'signal sel : integer:= 0;-Outputssignal x : std_logic_vector(7 downto 0);-No clocks detected in port list. Replace <clock> below with-appropriate port nameBEGIN-Instantiate the Unit Under Test (UUT) uut: decoder3 PORT MAP (ena => ena, sel

33、 => sel, x => x);-Stimulus processstim_proc: process begin-hold reset state for 100 ns.ena<='1' sel<=1;wait for 100 ns;ena<='1' sel<=0;wait for 100 ns;ena<='1' sel<=1;wait for 100 ns;ena<='1' sel<=0;wait for 100 ns;ena<='1' sel

34、<=2;wait for 100 ns;ena<='1' sel<=1;wait for 100 ns;ena<='1' sel<=2;wait for 100 ns;-insert stimulus herewait;end process;END;沅= L如图。如图。让使能端始终为“ 1”。当输入信号sel为“1”时，输出信号x 为“11111101”；当输入信号sel为“0”时，输出信号x为“11111110”；当 输入信号sel为“1”时，输出信号x为“11111101”；当输入信号sel为“0” 时，输出信号x为“1111

35、1110'当输入信号sel为“10”时，输出信号x 为“11111011”；当输入信号sel为“1”时，输出信号x为“11111101”；当 输入信号sel为“10”时，输出信号x为“11111011”。习题5.1通用多路复用器在例5.1和例5.2给出的多路复用器中，输入矢量的个数和每个输入矢量矢 量，m代表每个输入矢量的位宽。如图所示，电路有 2n个输入（注意这里的 n和m没有依赖关系）。试用GENERI鳍句来指定n的值，并假设m=8.实现这 个电路。图P54实验完整VHDL弋码：library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity mux1

36、 isGENERIC (n: INTEGER :=2;m: INTEGER :=7);Port ( a : in STD LOGIC VECTOR(m DOWNTO 0);b : in STD_LOGIC_VECTOR(m DOWNTO 0);c : in STD_LOGIC_VECTOR(m DOWNTO 0);d : in STD_LOGIC_VECTOR(m DOWNTO 0);e : in STD_LOGIC_VECTOR(m DOWNTO 0);f : in STD_LOGIC_VECTOR(m DOWNTO 0);g : in STD_LOGIC_VECTOR(m DOWNTO 0

37、);h : in STD_LOGIC_VECTOR(m DOWNTO 0);sel : in STD_LOGIC_VECTOR(n DOWNTO 0);Y : out STD_LOGIC_VECTOR(m DOWNTO 0); end mux1;architecture Behavioral of mux1 is beginY <= a WHEN sel="000" ELSEb WHEN sel="001" ELSEc WHEN sel="010" ELSEd WHEN sel="011" ELSEe WHE

38、N sel="100" ELSEf WHEN sel="101" ELSEg WHEN sel="110" ELSE h;02end architecture;仿真测试文件代码：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY mux2 ISEND mux2;ARCHITECTURE behavior OF mux2 IS-Component Declaration for the Unit Under Test (UUT)COMPONENT mux1PORT(a : IN std_log

39、ic_vector(7 downto 0);b : IN std_logic_vector(7 downto 0);c : IN std_logic_vector(7 downto 0);d : IN std_logic_vector(7 downto 0);e : IN std_logic_vector(7 downto 0);f : IN std_logic_vector(7 downto 0);g : IN std_logic_vector(7 downto 0);h : IN std logic vector(7 downto 0);sel : IN std_logic_vector(

40、2 downto 0);Y : OUT std_logic_vector(7 downto 0)；END COMPONENT;-Inputssignal a :std_logic_vector(7downto0):= (others => '0');signal b :std_logic_vector(7downto0):= (others => '0');signal c :std_logic_vector(7downto0):= (others => '0');signal d :std_logic_vector(7down

41、to0):=(others => '0');signal e :std_logic_vector(7downto0):=(others => '0');signal f : std_logic_vector(7 downto 0) := (others => '0');signal g :std_logic_vector(7downto0):=(others => '0');signal h :std_logic_vector(7downto0):=(others => '0');si

42、gnal sel : std_logic_vector(2 downto 0) := (others => '0');-Outputssignal Y : std_logic_vector(7 downto 0);-No clocks detected in port list. Replace <clock> below with- -appropriate port nameBEGIN- -Instantiate the Unit Under Test (UUT) uut: muxl PORT MAP (a => a, b => b, c =&

43、gt; c, d => d, e => e, f => f, g => g, h => h, sel => sel, Y => Y);-Stimulus processstim_proc: processbegin- -hold reset state for 100 ns.sel<=''000" a<="00000000" b<="0011000T' c<="10101000”; d<="01010111" e<=&quo

44、t;11110000" f<="01110011" g<="00110011”; h<=”11111111”;wait for 100 ns;sel<="001" a<="00000000" b<="0011000T' c<="10101000”; d<="01010111" e<="11110000" f<="01110011" g<="0011001

45、1”; h<=”11111111”；wait for 100 ns;sel<="100“； a<="00000000“； b<="0011000T' c<="10101000”； d<="01010111“； e<="11110000“； f<="01110011“； g<="00110011”； h<=”11111111”；wait for 100 ns;sel<="010"； a<="00000000&

46、quot;； b<="00110001"； c<="10101000”； d<="01010111"； e<="11110000"； f<="01110011"； g<="00110011”； h<二”11111111”；wait for 100 ns;sel<="011"； a<="00000000"； b<="00110001"； c<="10101000”

47、; d<="01010111"； e<="11110000"； f<="01110011"； g<="00110011”； h<二”11111111”；wait for 100 ns;sel<="111"； a<="00000000"； b<="00110001"； c<="10101000”; d<="01010111"； e<="11110000"

48、； f<="01110011"； g<="00110011”； h<二”11111111”；wait for 100 ns;sel<="101"； a<="00000000"； b<="00110001"； c<="10101000”; d<="01010111"； e<="11110000"； f<="01110011"； g<="00110011”； h&l

49、t;二”11111111”；wait for 100 ns;- -insert stimulus herewait;end process;END;如图。假设输入的各种信号为 a<="00000000", b<="00110001”, c<="10101000" , d<="01010111", e<="11110000", f<="01110011”, g<="00110011", h<="iiiiiiii"

50、;0 当输入信号 sel 为 “000” 时，输出信号 Y 等于a信号等于“ 00000000'当输入信号sel为“001”时，输出信号Y等 于b信号等于“ 00110001”；当输入信号sel为“100”时，输出信号Y等于 e信号等于“ 11110000'当输入信号sel为“010”时，输出信号Y等于c 信号等于“ 10101000'当输入信号sel为“011”时，输出信号Y等于d信 号等于“01010111”；当输入信号sel为“111”时，输出信号Y等于h信号 等于“11111111”；当输入信号sel为“101”时，输出信号Y等于f信号等 于 “01110011

51、”。习题5.5有符号数/无符号数加法器和减法器与习题5.4相比，图P5.5所示的电路增加了一个两位的输入信号（sel）, 这样电路就可以有选择的执行有符号数/无符号数加法运算或减法运算（见真 值表）。试编写VHDL弋码实现这个电路。a (7:0)sum (7:0)b (7:0)sel (kO)sel运算00无符号加法01带符号加法10无符号减法11带符号减法图 P5.5实验完整VHDL弋码：library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std logic unsigned.all;u

52、se ieee.std_logic_signed.all;entity adderminus isport(a,b:in unsigned。downto 0);sel:in bit_vector(1 downto 0);sum:out std_logic_vector(8 downto 0);end;architecture bhv of adderminus issignal temp1,temp2:unsigned (8 downto 0);signal temp3,temp4:signed(8 downto 0);-signal an,as,sn,ss:std_logic_vector(

53、8 downto 0);signal a0,b0:signed (7 downto 0);signal cin0:std_logic_vector(7 downto 0);begina0<=conv_signed(a,8);b0<=conv_signed(b,8);temp1<=conv_unsigned(a+b),9);temp2<=conv_unsigned(a-b),9);temp3<=conv_signed(a0+b0),9);temp4<=conv_signed(a0-b0),9);sum<=conv_std_logic_vector(tem

54、p1,9)when sel="00" else conv_std_logic_vector(temp3,9)when sel="01" else conv_std_logic_vector(temp2,9)when sel="10" else conv_std_logic_vector(temp4,9);end;仿真测试文件代码：LIBRARY ieee;USE ieee.std_logic_1164.ALL;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;us

55、e ieee.std_logic_signed.all;ENTITY Test_adderminus ISEND Test_adderminus;ARCHITECTURE behavior OF Test_adderminus IS-Component Declaration for the Unit Under Test (UUT)COMPONENT adderminusPORT(a : IN unsigned(7 downto 0);b : IN unsigned(7 downto 0);sel : in bit vector(1 downto 0);sum : out std_logic

56、_vector(8 downto 0)；END COMPONENT;-Inputssignal a : unsigned。downto 0);signal b : unsigned。downto 0);signal sel : bit_vector(1 downto 0);-Outputssignal sum : std_logic_vector(8 downto 0);-No clocks detected in port list. Replace <clock> below with-appropriate port nameBEGIN-Instantiate the Uni

57、t Under Test (UUT) uut: adderminus PORT MAP (a => a, b => b, sel => sel, sum => sum);-Stimulus process stim_proc: process begin-hold reset state for 100 ns.a<="00100000" b<="00001100" sel<="00"wait for 100 ns;a<="00100100" b<="0

58、1000110" sel<="01" wait for 100 ns;a<="11001100" b<="00110101" sel<="10" wait for 100 ns;a<="00110010" b<="00100000" sel<="11" wait for 100 ns;-insert stimulus herewait;end process;END;仿真结果:户 M JLE 111111

59、114闻 ha. 1 i b 1 a i >i i 1BSD DE 11111111BOO vie11 b 1D 111H *Q . L：001102oaioa:iioazoi:11E 001&QM0 X OOlM'di k llQOLLOoX"r o&iiaioi y-的100度心1。 pg Y 口i 、li Xl ： IrOCM_ 004 DE如图。当输入信号a为“0010000。，输入信号b为“0000110。，输入信号 sel为“00”，输出信号sum为“000101100'当输入信号a为“00100100', 输入信号b为“01

60、000110',输入信号sel为“01”，输出信号sum为“001101010'当输入信号 a 为 “11001100',输入信号 b 为 “00110101”，输入信号sel为“10”，输出信号sum为“010010111”；当输入信号a为 “00110010',输入信号b为“00100000',输入信号sel为“11”，输出信号sum为 “000010010'。习题5.6二进制码-格雷码转化器在数字系统中，我们用得最多的是二进制码。其最低位的权重是2°,权重按其尾数以2的指数归律递增，最高位的权重是 2n-1 （n是位宽）。另一方面

61、， 格雷码的相邻码字具有最小汉明距离。也就是说，相邻码字只有一位不同。当n=4时，我们在表P5.6中列出了 4位二进制码和格雷码的所有码字。 试编 写VHDL弋码，实现从二进制码到格雷码的准换功能（位宽n为GENERI参数, 以增加电路的通用性）。表 P5.6二进制编向一 格雷向000000000001000100100011001100100100011001010111I0110010101110100100011001001L101101011111011U1011001010iioiion1110100111111000实验完整VHDL弋码：library IEEE;use IEEE.

62、STD_LOGIC_1164.ALL;entity grey isPort ( a : in STD_LOGIC_VECTOR(3 DOWNTO 0); c : out STD_LOGIC_VECTOR(3 DOWNTO 0); end grey;architecture Behavioral of grey isbeginc<="0000" WHEN a<="0000" ELSE"0001" WHEN a<="0001" ELSE"0011" WHEN a<="

63、;0010" ELSE"0010" WHEN a<="0011" ELSE"0110" WHEN a<="0100" ELSE"0111" WHEN a<="0101" ELSE"0101" WHEN a<="0110" ELSE"0100" WHEN a<="0111" ELSE"1100" WHEN a<="1000"