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1、.江苏科技大学电子信息学院数字电子技术实验课 程 设 计 报 告指导老师 : 李绍鹏学 院: 电子信息学院班 级: 11403022学生(学号): 孙磊(1140302219)目 录课题一 数字电子钟课题二 交通灯控制逻辑电路设计(注:由于Quartusii 9.0不支持中文输入,但支持中文复制,所以以下代码文字说明均为后期制作)课题一 数字电子钟任务:用文本法设计一个能显示时、分、秒的数字电子钟要求:1.设计由20mhz有源晶振电路产生标准信号的单元电路; 2.时为0023六十进制计数器,分、秒为0059六十进制计数器; 3.能够显示出时、分、秒; 4.具有清零,调节分钟的功能; 5.模拟钟
2、摆功能; 6.具有整点报时功能,整点报时的同时声响电路发出叫声; 7.对时、分、秒单元电路进行仿真并记录。本文利用Verilog HDL语言自顶向下的设计方法设计多功能数字钟,并通过仿真和下载,实现其基本功能。1 顶层文件 module top(CLK,SET,EN,RE, /CLK=20M HZ SET调节分钟LED_5,OUT,QH1,QH0,QM1,QM0,QS1,QS0); input CLK,SET,RE,EN; output OUT; /OUT报时 output 3:0 QH1,QH0,QM1,QM0,QS1,QS0; output 4:0 LED_5; wire clk1khz,
3、clk250hz,clk1hz,m1,b2,b3,b4; wire 5:0 s1,m2,h3;/-分频- Div u1(CLK,EN,RE,14'd6384,clk1khz); Div u2(clk1khz,EN,RE,14'd16382,clk250hz); Div u3(clk1khz,EN,RE,14'd15884,clk1hz); /-秒s1计数 ,产生分进位m1- counter u4(clk1hz,EN,RE,6'd59,m1,s1); BCDturn u5(s1,QS1,QS0); /-分m2计数,产生时进位b3- counter u6(b2,EN
4、,RE,6'd59,b3,m2); BCDturn u7(m2,QM1,QM0); /-时h3计数,产生进位b4- counter u8(b3,EN,RE,6'd23,b4,h3); BCDturn u9(h3,QH1,QH0); /-模拟钟摆- led_ u10(CLK,LED_5); /-整点报时- baoshi u11(QM1,QM0,QS1,QS0,OUT);/-b2调节分钟- assign b2=SET?SET:m1; endmodule2 分频模块module Div(CLK,EN,RE,d,Q); /给d赋初始值 input CLK,EN,RE; input 13
5、:0 d; output Q; reg FULL,Q; reg 13:0 c; always(posedge CLK ) begin if(RE) begin c<=d; FULL<=0; end else if(EN) begin if(c=141'b1) begin c<=d; FULL<=1; end else begin c<=c+1; FULL<=0; end end end always(posedge FULL) /得到占空比50%的分频信号 begin Q<=Q; endendmodule3 计数模块module counter
6、(CLK,EN,RE,C,FULL,Q); /EN=1时进行计数,RE=1时清零 input CLK,EN,RE; /C表示N进制,Q为计数结果 input 5:0 C; output 5:0Q; output FULL; reg 5:0Q; reg FULL; always(posedge CLK) begin if(RE) begin Q<=0; FULL<=0; end else if(EN) begin if(Q=C) begin Q<=0; FULL<=1; end else begin Q<=Q+1; FULL<=0; end end end e
7、ndmodule4 BCD译码模块/由于计数使用的二进制,在输出时便需要进行译码,转换成大众所熟悉的十进制表示module BCDturn(indec,qh,ql); input 5:0 indec; output 3:0 qh,ql; reg 3:0 qh,ql; always(indec) begin case(indec)6'd0:begin qh3:0<='b0000;ql3:0<='b0000;end6'd1:begin qh3:0<='b0000;ql3:0<='b0001;end6'd2:begin
8、qh3:0<='b0000;ql3:0<='b0010;end6'd3:begin qh3:0<='b0000;ql3:0<='b0011;end6'd4:begin qh3:0<='b0000;ql3:0<='b0100;end6'd5:begin qh3:0<='b0000;ql3:0<='b0101;end6'd6:begin qh3:0<='b0000;ql3:0<='b0110;end6'd7:begin
9、qh3:0<='b0000;ql3:0<='b0111;end6'd8:begin qh3:0<='b0000;ql3:0<='b1000;end6'd9:begin qh3:0<='b0000;ql3:0<='b1001;end6'd10:begin qh3:0<='b0001;ql3:0<='b0000;end6'd11:begin qh3:0<='b0001;ql3:0<='b0001;end6'd12:beg
10、in qh3:0<='b0001;ql3:0<='b0010;end6'd13:begin qh3:0<='b0001;ql3:0<='b0011;end6'd14:begin qh3:0<='b0001;ql3:0<='b0100;end6'd15:begin qh3:0<='b0001;ql3:0<='b0101;end6'd16:begin qh3:0<='b0001;ql3:0<='b0110;end6'd1
11、7:begin qh3:0<='b0001;ql3:0<='b0111;end6'd18:begin qh3:0<='b0001;ql3:0<='b1000;end6'd19:begin qh3:0<='b0001;ql3:0<='b1001;end6'd20:begin qh3:0<='b0010;ql3:0<='b0000;end6'd21:begin qh3:0<='b0010;ql3:0<='b0001;end6
12、39;d22:begin qh3:0<='b0010;ql3:0<='b0010;end6'd23:begin qh3:0<='b0010;ql3:0<='b0011;end6'd24:begin qh3:0<='b0010;ql3:0<='b0100;end6'd25:begin qh3:0<='b0010;ql3:0<='b0101;end6'd26:begin qh3:0<='b0010;ql3:0<='b0110;e
13、nd6'd27:begin qh3:0<='b0010;ql3:0<='b0111;end6'd28:begin qh3:0<='b0010;ql3:0<='b1000;end6'd29:begin qh3:0<='b0010;ql3:0<='b1001;end6'd30:begin qh3:0<='b0011;ql3:0<='b0000;end6'd31:begin qh3:0<='b0011;ql3:0<='b0
14、001;end6'd32:begin qh3:0<='b0011;ql3:0<='b0010;end6'd33:begin qh3:0<='b0011;ql3:0<='b0011;end6'd34:begin qh3:0<='b0011;ql3:0<='b0100;end6'd35:begin qh3:0<='b0011;ql3:0<='b0101;end6'd36:begin qh3:0<='b0011;ql3:0<=
15、39;b0110;end6'd37:begin qh3:0<='b0011;ql3:0<='b0111;end6'd38:begin qh3:0<='b0011;ql3:0<='b1000;end6'd39:begin qh3:0<='b0011;ql3:0<='b1001;end6'd40:begin qh3:0<='b0100;ql3:0<='b0000;end6'd41:begin qh3:0<='b0100;ql3:0&l
16、t;='b0001;end6'd42:begin qh3:0<='b0100;ql3:0<='b0010;end6'd43:begin qh3:0<='b0100;ql3:0<='b0011;end6'd44:begin qh3:0<='b0100;ql3:0<='b0100;end6'd45:begin qh3:0<='b0100;ql3:0<='b0101;end6'd46:begin qh3:0<='b0100;ql
17、3:0<='b0110;end6'd47:begin qh3:0<='b0100;ql3:0<='b0111;end6'd48:begin qh3:0<='b0100;ql3:0<='b1000;end6'd49:begin qh3:0<='b0100;ql3:0<='b1001;end6'd50:begin qh3:0<='b0101;ql3:0<='b0000;end6'd51:begin qh3:0<='b01
18、01;ql3:0<='b0001;end6'd52:begin qh3:0<='b0101;ql3:0<='b0010;end6'd53:begin qh3:0<='b0101;ql3:0<='b0011;end6'd54:begin qh3:0<='b0101;ql3:0<='b0100;end6'd55:begin qh3:0<='b0101;ql3:0<='b0101;end6'd56:begin qh3:0<=
19、9;b0101;ql3:0<='b0110;end6'd57:begin qh3:0<='b0101;ql3:0<='b0111;end6'd58:begin qh3:0<='b0101;ql3:0<='b1000;end6'd59:begin qh3:0<='b0101;ql3:0<='b1001;enddefault:begin qh3:0<='bx;ql3:0<='bx;endendcaseendEndmodule5 模拟钟摆模块/该模块对
20、20mhz的clk进行的分频,所得到的8hz(clk_8hz)用作5个LED的时钟脉冲module led_(clk,ledout);input clk;output4:0ledout;reg4:0ledout;reg12:0count0;reg clk_2khz,clk_8hz;reg6:0count4;reg2:0cnt1;always(posedge clk)beginif(count0='d5000) /5000begin clk_2khz<=clk_2khz;count0<=0;endelsebegincount0<=count0+1;endendalway
21、s(posedge clk_2khz)beginif(count4='d125) /125beginclk_8hz<=clk_8hz;count4<=0;endelsebegincount4<=count4+1;endendalways(posedge clk_8hz)beginif(cnt1='d7)begincnt1<='d0;endelsebegincnt1<=cnt1+1;endendalways(cnt1)begincase(cnt1)3'd0:ledout4:0<=5'b10000;3'd1:led
22、out4:0<=5'b01000;3'd2:ledout4:0<=5'b00100;3'd3:ledout4:0<=5'b00010;3'd4:ledout4:0<=5'b00001;3'd5:ledout4:0<=5'b00010;3'd6:ledout4:0<=5'b00100;3'd7:ledout4:0<=5'b01000;endcaseendendmodule6 整点报时模块/该模块在49:52,49:54,49:56,49:5800:00
23、这6个秒段产生高电平,用作报时module baoshi(qmh,qml,qsh,qsl,OUT); input3:0 qmh,qml,qsh,qsl; output OUT; reg OUT;always( qmh or qml or qsh or qsl)begin if(qmh=4'd5&&qml=4'd9&&qsh=4'd5&&qsl=4'd2)OUT<=1;else if(qmh=4'd5&&qml=4'd9&&qsh=4'd5&&am
24、p;qsl=4'd4)OUT<=1;else if(qmh=4'd5&&qml=4'd9&&qsh=4'd5&&qsl=4'd6)OUT<=1;else if(qmh=4'd5&&qml=4'd9&&qsh=4'd5&&qsl=4'd8)OUT<=1;else if(qmh=4'd5&&qml=4'd9&&qsh=4'd5&&qsl=4
25、39;d9)OUT<=1;else if(qmh=4'd0&&qml=4'd0&&qsh=4'd0&&qsl=4'd0)OUT<=1;else OUT<=0;endendmodule逻辑功能仿真结果:调节分钟:模拟钟摆:通过以上仿真,在实验板上进行测试,管脚锁定:实验最终测试运行良好,并通过验收。课题二 交通灯控制逻辑电路设计任务:用CPLD设计路口交通灯控制器要求:1.满足如下时序要求:南北方向红灯亮,东西方向绿灯亮;南北方向绿灯亮,东西方向红灯亮; 2.每一方向的红(绿)黄灯总共维持30秒;
26、3.十字路口要有时间显示,具体为:当某一方向绿灯亮时,置显示器为30秒,然后以每秒减一计数方式工作,直至减到数为4秒时,红绿灯熄灭,黄灯开始间隙闪耀4秒,减到零时,红绿灯交换,一次工作循环结束,进入下一步另一方向的工作循环; 4.红绿黄灯均采用发光二极管; 5.设计由晶振电路产生1Hz标准秒信号的单元电路; 6.要求对整体电路进行仿真,观察并记录下仿真波形; 7.东西方向或南北方向的绿灯亮变为红灯亮,中间需插入黄灯闪耀4秒过渡,而从红灯亮变为绿灯亮,不需要黄灯过渡,直接由红灯变为绿灯。文本文件:module traffic(qh,ql,clk,clr,enmergy,ra,ya,ga,rb,y
27、b,gb);output ra,ya,ga,rb,yb,gb; /东西方向红(ra)黄(ya)绿(ga);南北方向红(rb)黄(yb)output3:0 qh,ql; /绿(gb) input clk,clr,enmergy; /enmergy 紧急信号,该信号有效时,所有交通灯皆显红灯reg1:0state,next_state;parameter state0=2'b00,state1=2'b01,state2=2'b10,state3=2'b11;reg clk_1khz,clk_1hz,clk_2hz;reg3:0 qh,ql;reg r1,r2,g1,
28、g2,y1,y2;reg ra,ya,ga,rb,yb,gb;reg13:0count1;reg8:0count2,count3;reg a;reg4:0timer;always(posedge clk)beginif(count1=14'd10000) /10000beginclk_1khz<=clk_1khz;count1<=0;endelsebegincount1<=count1+1;endendalways(posedge clk_1khz)beginif(count2=9'd500) /500beginclk_1hz<=clk_1hz;coun
29、t2<=0;endelsebegincount2<=count2+1;endif(count3='d250) /250beginclk_2hz<=clk_2hz;count3<=0;endelsebegincount3<=count3+1;endendalways(posedge clk_1hz)beginif(clr)beginr1<=0;y1<=0;g1<=0;r2<=0;y2<=0;g2<=0;endelsebeginstate=next_state;case(state)state0:beginif(!enmer
30、gy)beginif(!a)begintimer<=5'd30;a<=1;r1<=0;y1<=0;g1<=1;r2<=1;y2<=0;g2<=0;endelsebeginif(timer=1)beginnext_state<=state1;a<=0;timer<=0;endelsetimer<=timer-1;endendendstate1:beginif(!enmergy)beginif(!a)begintimer<=5'd4;a<=1;r1<=0;y1<=1;g1<=0;r
31、2<=1;y2<=0;g2<=0;endelsebeginif(timer=1)beginnext_state<=state2;a<=0;timer<=0;endelsetimer<=timer-1;endendendstate2:beginif(!enmergy)beginif(!a)begintimer<=5'd25;a<=1;r1<=1;y1<=0;g1<=0;r2<=0;y2<=0;g2<=1;endelsebeginif(timer=1)beginnext_state<=state
32、3;a<=0;timer<=0;endelsetimer<=timer-1;endendendstate3:beginif(!enmergy)beginif(!a)begintimer<=5'd4;a<=1;r1<=1;y1<=0;g1<=0;r2<=0;y2<=1;g2<=0;endelsebeginif(timer=1)beginnext_state<=state0;a<=0;timer<=0;endelsetimer<=timer-1;endendendendcaseendendalways
33、(enmergy,clk_1hz,r1,r1,g1,g1,y1,y2)beginif(enmergy)beginra<=r1|enmergy;rb<=r2|enmergy;ga<=g1&&enmergy;gb<=g2&&enmergy;ya<=y1&&enmergy;yb<=y2&&enmergy;endelsebeginra<=r1;rb<=r2;ga<=g1;gb<=g2;ya<=y1;yb<=y2;endendalways (timer)begincas
34、e(timer)5'd0:begin qh3:0<=4'b0000;ql3:0<='b0000;end5'd1:begin qh3:0<=4'b0000;ql3:0<='b0001;end5'd2:begin qh3:0<=4'b0000;ql3:0<='b0010;end5'd3:begin qh3:0<=4'b0000;ql3:0<='b0011;end5'd4:begin qh3:0<=4'b0000;ql3:0<=&
35、#39;b0100;end5'd5:begin qh3:0<=4'b0000;ql3:0<='b0101;end5'd6:begin qh3:0<=4'b0000;ql3:0<='b0110;end5'd7:begin qh3:0<=4'b0000;ql3:0<='b0111;end5'd8:begin qh3:0<=4'b0000;ql3:0<='b1000;end5'd9:begin qh3:0<=4'b0000;ql3:0&
36、lt;='b1001;end5'd10:begin qh3:0<='b0001;ql3:0<='b0000;end5'd11:begin qh3:0<='b0001;ql3:0<='b0001;end5'd12:begin qh3:0<='b0001;ql3:0<='b0010;end5'd13:begin qh3:0<='b0001;ql3:0<='b0011;end5'd14:begin qh3:0<='b0001;q
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