数字设计 第6章组合逻辑设计实践ppt课件

1、Chapter 6 Combinational Logic Design PracticesMSI building blocks are the important element of combinational circuits.本章重点n具备一定功能的通用组合逻辑电路的设计方法及实例n掌握常用的MSI的运用方法及功能扩展n掌握译码器、MUX实现组合逻辑功能的方法n能分析、设计由MSI构建的电路6.1 Documentation Standard1. Signal Names and Active LevelsMost signals (signal name) have active

2、level. active high active lowNaming convention surffix “_L attaching to signal name represent active low level. Like, EN_L、READY_L In logic relation, EN_L=EN， READY_L=READY。2. Active levels for pinsENEN_LDinstartDoutflgstart_LDinDoutflg_LInversion bubbleActive lowENENDinstartDoutflgstartDinDoutflgAc

3、tive hignExp2：EN=1 (active high), data can be transferredEN=0 (active low), data can be transferredENCLKEN_LCLK3. bubble-to-bubble logic designMake the logic circuit easier to understand.Exp：Not matchNot matchABSELDATAABASELDATAmatchmatch6.3 Combinational PLDs1. Programmable logic arrays (PLA) two l

4、evel “ANDORdevice. Can be programmed to realize any sum-of-products logic expression.An nm PLA with p product terms: ninputs moutputs pproduct terms43 with 6 product termsAND array2. Programmable Array Logic DevicesFixed OR array，programmable AND arrayBidirectional input/output pins，熔丝型PAL16L8，Outpu

5、t enable3. Generic Array Logic DevicesGALan innovation of the PAL; can be erased and reprogrammed; 6.4 DecodernAn important type of combinational circuit .input code wordenable inputOutput code word decodeer1-to-1mapping1-out-of-m codenmn-bitm-bit1、bianry decodersninput code：n-bitnoutput code：2n-bit

6、n 2-4 decoder2-22n I1I0Y3Y2Y1Y0truth table：？：？Yi：？：？I1I0Y3 Y2 Y1 Y0000001010010100100111000Yi=miY0=I1I0Y1=I1I0Y2=I1I0Y3=I1I02-4decoderOne input combination chooses an output port.n2-4 decoder with enable inputnYi=EN miENI1I0Y3Y2Y1Y00 00001000001101001011001001111000I1I0Y3Y2Y1Y0EN2-4 decoder274 , dua

7、l 2-4 decoderInput code：BMSB ALSBAlso be called address input.Output code：Y3_LY0_LEN 374, 3-8 decoderuEnable inputuEN=G1G2A_LG2B_LuInput code：uCMSB、B、 AuOutput code：u Y0_L Y7_LuYi_L=ENmiY0_LY1_LY2_LY3_L Y4_L Y5_L Y6_L Y7_LG1G2A_LG2B_LENENmsblsb2、realizing combinational circuits with decodernreview：c

8、anonical sumnDecoder output：Yi_L=(ENmi) n when EN=1， Yi_L=mi =Min add an NAND gate to the decoders output.nExp: (1) F=AB0、3F=AB+ABEnable asserted2if a 3-bit number XYZ is odd number，then ODD output 1，else output 0. realize the function with decoder and gates.solution：F=？F=XYZ1，3，5，73F=XYZ0、1、5 解：解：3

9、. Cascading binary decodersnHow to construct a 4-16、5-32 decoder？n use multiple 2-4 or 3-8 decoders to cascade.nPS.：nconfirm the number of decoders according to the input and output bits.nonly one chip works in each decoding operation.Exp：a 4-16 decoderInputs: 4-bit N3、N2、N1、N0。Outputs: 16-bit DEC15

10、_LDEC0_LNeed 2 3-8 decoders. Use the MSB of the inputs as chip-select bit. 000000010111100010011111N3 N2 N1 N0N3 N2 N1 N0Chip selectingnExp：4-bit prime-number detector. Realizing it with 74 and some gates.N3N2N1N0U174HC138D_6VY015Y114Y213Y312Y411Y510Y69Y77A1B2C3G16G2A4G2B5U274HC138D_6VY015Y114Y213Y3

11、12Y411Y510Y69Y77A1B2C3G16G2A4G2B5U374HC30D_6VR1 1kR21kVCC5VGNDGNDF4、7-segment decoderClassify of 7-seg displayer：in materials: LED发光二极管发光二极管 LCD液晶液晶In working mode: common-cathode (共阴极共阴极) common-anode (共阳极共阳极)afbcegddpabcdedpfggndgnd 7-segment decoder transform the input BCD code to 7-segment displ

12、aying code. devices： 7446A、74LS47 驱动共阳驱动共阳 74LS48、 74LS49驱动共阴驱动共阴8ADCBLTNBINRBINOBOCODOEOFOGRBONOA7448BCD TO 7SEG6CABDBINODOCOBOGOFOEOA7449BCD TO 7SEG00001001 are useful input codes.10101111 are unused BCD code.U1A5B1C2D4OA11OD8OE6OF13OC9OB10OG12BI3U2A B C D E F GCKHGNDVCCR1R6R7R8R9R10 R1174LS495、BC

13、D decoder二二十进制译码器十进制译码器Inputs: BCDY0Y9BCD decoderOutput:1-out-of 10 code9DCBAO0NO1NO2NO3NO4NO5NO6NO7NO8NO9N7442BC D TO D EC74HC425.5 Encoder1、binary encoder inputs:1-out-of-2n codeI0I1Im(m=2n-1) output:n-bitY0Y1Yn-1binary encoder8-3 encoderinputoutputI7I6I5I4I3I2I1I0Y2Y1Y0100000001110100000011000100

14、0001010001000010000001000011000001000100000001000100000001000In/out:active highY0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I7Each input port has its corresponding output code.2、Priority Encoder if multiple inputs are asserted, how to deal with? solution：assign priority to each input from high to low. le

15、t I7 highest priority and decrease from I6 down to I0 A2,A1,A0encode output IDLEwhen no input is asserted, IDLE=1inputoutputI7I6I5I4I3I2I1I0A2A1A0IDLE11110011100001101000011000000010110000001010000000010010000000010000000000000001Logic expressions for priority encoderH7=I7H6=I6I7H5=I5I6I7H0=I0I1I2I3

16、I4I5I6I7A2=H4+H5+H6+H7A1=H2+H3+H6+H7A0=H1+H3+H5+H7IDLE=(I0+I1+I2+I3+I4+I5+I6+I7) =I0I1I2I3I4I5I6I7Expressions for each asserted input in the truth table of priority encoderOutput code expressions 3、74148 Priority Encoder EI_L：Enable Input. I7_LI0_L：encode input，I7_L has highest priority. A2_LA0_L：en

17、code output GS_L：GS_L =0 when one or more of the request inputs are asserted. EO_L：enable output, EO_L=0 when all of the request inputs are negative and EI_L=0. 高高低低优先级优先级n74148真值表真值表4、cascading priority encoderproblem：how to construct 16-4、32-5 priority encoder？Connecting multiple 8-3 endoder.note：

18、make sure the needed number of chips according to the inputs.need to redesign the output circuit that could produce the correct encoding output.n16-4 priority encoder:n use two 74148 U1、U2，n(1) U1: input E15_LE8_L;n U2: input E7_LE0_L;n E15_L is the highest priority,n(2) output: A3_LA0_L，active low;

19、n(3) When one or more inputs is asserted，GS0_L=0；and A3_LA0_L=1111.16-4 priority encoderU174HC148A09A110A211GS14D34D45D56D23D12D78D67EI12EO13U274HC148A09A110A211GS14D34D45D56D23D12D01D78D67EI12EO13U3A74HC08U3B74HC08U3C74HC08U3D74HC08D01EN15_LEN14_LEN13_LEN12_LEN11_LEN10_LEN9_LEN8_LEN7_LEN6_LEN5_LEN4

20、_LEN3_LEN2_LEN1_LEN0_LD0_LD1_LD2_LD3_LGS_Ln思索：假设需求编码输出、GS0为高电平有效，如何修正电路输出构造？nP.413 figure 6-49 shows the 32-5 priority encoders strcture,.6.6 Three-state Devices1、three-state buffersEnable means: the buffer output normal logic 0、1 when EN is asserted；the buffer output Hi-Z when EN is negated. lAppli

21、cation data address of data sourcelIssues in applicationl TPLZ 、TPHZ ：time that takes from normal logic into Hi-Z;l TPZL 、TPZH ：time that takes from Hi-Z into normal logic;lgenerally， TPLZ 、TPHZ TPZL 、TPZH lBut to confirm the correction in application, a control logic is adopted.74的相的相关引关引脚信脚信号号 截止时

22、间截止时间停滞时间停滞时间课堂练习课堂练习n试设计一个电路，当控制信号试设计一个电路，当控制信号M=1时，电路为时，电路为“判一致电路，即当三个输入变量取值全部一判一致电路，即当三个输入变量取值全部一样时输入为样时输入为1；当控制信号；当控制信号M=0时，电路为时，电路为“多数多数表决电路，即输出等于输入变量中占多数的取表决电路，即输出等于输入变量中占多数的取值。请写出最简表达式。注：至少要写出卡诺值。请写出最简表达式。注：至少要写出卡诺图，三变量为图，三变量为X、Y、Z6.7 Multiplexer2-to-1 MUXABSELYY=SELA+SELBS=0， Y=AS=1，Y=BABS=0

23、Y=AABS=1Y=BLogic circuit又称数据选择器，简称MUXOutput:enableselect n data source data output10(1)njjjiYEN m iDib gg n2s mj：SELj minterm1、根本构造：、根本构造：Let b=1, 10njjjYEN m DggD0D1DjDn-1SELENExp:4-to-1 MUXABCDS1S001101234outputCS0S1output00A01B10C11D2、MSI MUX18-to-1 MUX ，74151EN_LaddressY_LY70jjjYEN m Dgg24-bit,

24、2 input MUX ，7415732 bit, 4 input MUX，74 15392Y1Y1C11C01GN2C02GN1C31C22C22C1AB2C374153MULTIPLEXERinputoutput1G_L2G_LBA1Y2Y00001C02C000011C12C100101C22C200111C32C301001C0001011C1001101C2001111C30100002C0100102C1101002C2101102C311001G_L2G_L3、Expanding MUXsExp1：use 74151 to realize a 16-to-1 MUX, some

25、gates can be used if necessary.Chips needed： according to the 16 inputs, 2 74151 chips.output： combine two chips outputs into one output.The MSB(A3) of input act as the chip-select bit.Exp2：用：用74153实现实现4输入，输入，4位位MUX，。，。 设设4路输入分别是：路输入分别是：1D3.0、2D3.0、3D3.0、4D3.0； 4位输出是：位输出是：Dout3.0 输入选择：输入选择：S1、S0解：无需

26、外加门，只需求合理安排输入、输出数据解：无需外加门，只需求合理安排输入、输出数据端口即可。端口即可。S1S04、用、用MUX实现组合逻辑函数的规范和实现组合逻辑函数的规范和 multiple input, 1 bit MUX, the output： when EN is asserted： the canonical sum form.10njjjYEN m Dgg10njjjYm Dgmj: minterm of the select (address) inputs. MUX的数据输入端与真值表的每行输出对应，的数据输入端与真值表的每行输出对应，MUX的地址选择端作为最小项产生器，即的地

27、址选择端作为最小项产生器，即 真值表：输出值真值表：输出值输入变量输入变量 MUX：数据输入端：数据输入端地址端地址端 Exp1：a circuit output 1 when its 3-bit input can be divided by 3. construct the circuit by using 74151. So：F=XYZ？ and circuit？按最小项编号顺序按最小项编号顺序变量与选择端对应变量与选择端对应n例例1的电路的电路XYZFU1W6D04D13D22D31D415D514D613D712S011S29S110Y5G7VCCGNDR1例例2：假设例：假设例1中

28、输入数为中输入数为4位二进制数，如何实现？位二进制数，如何实现？解解1：用：用16输入，输入，1位的位的MUX来实现，选用来实现，选用74150。 F=WXYZ0，3，6，9，12，15解解2：仍选用：仍选用74151，先对所求函数的卡诺图做，先对所求函数的卡诺图做降维处置。降维处置。预备知识：卡诺图的降维预备知识：卡诺图的降维 用一个用一个n变量的卡诺图来处置变量的卡诺图来处置m变量的函数变量的函数nB)F(A=B)F(AB= ABFABFABFA=BFAB=(A1B1)+(A1=B1) ( A0B0) = A1B1 + (AB+AB)(A1B1 )FA=B=(A1=B1)(A0=B0)FA

29、B=(A1B1)+(A1=B1)(A0BFA=BFABA1B11A1=B1A0B01A1=B1A0=B01Pseudo-logic4. Standard MSI magnitude comparator7485: 4-bitMagnitude input: A3.0, B3.0Cascading input：ALBI、AEBI、AGBI，which are used to expanding comparator.output：ALBO、AEBO、AGBOAGBO=(AB)+(A=B)AGBIAEBO=(A=B)AEBIALBO=(ABFA=BFABFA=BFABX11.8Y11.8X7.4Y

30、7.4X3.0Y3.0Class exerciseABCDFDAADCDCABJudge whether the following circuit has static hazard or not, if static hazard exist, please point it and eliminate by using K-map. Then write the hazardless minimal sum.6.10 Adders、Subtractors and ALUnUsed to do binary addition and subtractionn1. Half adders and full addersn1half addersXYHSCO0000011010101101half sum：HS=X Ycarry-out：CO=XYXYHSCO2full addersCINXYSCO0000000110010100110110010101011100111111sum：S=X Y CINcarry：CO=XY+CINX+CINY2、ripple addersnUse 1-b