FlashMemory测试简介学习教案

1、会计学1FlashMemory测试简介测试简介第1页/共62页第2页/共62页第3页/共62页第4页/共62页第5页/共62页第6页/共62页第7页/共62页Word lineBit lineWord lineBit line第8页/共62页Word lineBit lineBit lineBit lineActivate Row to readIf capacitor was charged, no current flows on bit lineIf capacitor not charged, current flows on bit lineBuffer on column sens

2、e amps第9页/共62页Word lineBit lineBit lineBit line第10页/共62页Floating GateSourceGateDrain Floating Gate (electrically isolated) is the storage element charged = “programmed” neutral = “erased”第11页/共62页第12页/共62页第13页/共62页第14页/共62页第15页/共62页e-e-e-e-e-第16页/共62页VT (UV State)VT (Erased)VT (Programmed, Read)第17页

3、/共62页Core memory (core)第18页/共62页第19页/共62页1111000000000000A0A1A2A3A4A5A6A7Memory cellMemory Cell block: 每个CELL存储 data（1/0）Address Decoder Circuitry：地址译码 以(A0 )来选择不同的memory cell or block进行读写操作。Input/Output I/O) circuitry：是memory Cell 和外界的输入输出接口， 将data 在(D0 ) 与Cell间传输。Control Circuitry： 控制memory Cell 工

4、作状态的电路 CE/ OE/ WE (Chip Enable/ Output Enable / Write Enable)第20页/共62页第21页/共62页ISVM：Force current message voltageVSIM: Force voltage message currentDC Parametric Tests：测试 Address Decoder 和 I/O 回路 中Input/Output Buffer的DC特性。 在DC Test中一般使用 VSIM 及ISVM 的方法。DC Contact CheckDC Contact Check 开路/短路测试 OPEN/SH

5、ORTInput/Output Leakage CheckInput/Output Leakage Check 输入/输出漏电流测试 INLEAK/OUTLEAK CMOS Automatic Sleep CMOS Automatic Sleep CMOS自动睡眠模式电流测试 CMOSASM Standby Current CheckStandby Current Check Device不工作时待机电流测试 ICCSBOutput Drive Voltage & CurrentOutput Drive Voltage & Current Device 电压及电流驱动能力测试

6、VOH/VOL第22页/共62页第23页/共62页Purpose: 测量 device pins 是否 correctly to DUT/Tester channel 测量 Device内部 管脚是否有开路。Ground all pins (including VCC);Set Voltage Clamp 3.0 volts;Using PMU, force positive or negative current, one pin at a time;Measure resultant voltage;Fails test (open) if the absolute voltage mea

7、sured is greater than 1.5V;Test Method第24页/共62页Purpose: 测试 the device pins 是否有短路 Test Method:V s s ( 0 V)Vcc (3.3V)In (0.3V)No current t h r o u g h two p r o t e c t diodeIf short I 100uaI Vss (0 V)Vcc (3.3V)In (0.3V)No current through two protect diodeNormal I 1 transition when it is written is sa

8、id to contain an up transition fault; similarly, a down transition fault is the impossibility of making a 1 - 0 transition.第46页/共62页A write operation which generates an U or a Y transition in one cell changes the contents of a second cell, where U denotes a write 1 operation to a cell containing a 0

9、 and Y denotes a write 0 operation to a cell containing a 1.The types of coupling faults used for DRAM are based on the following assumptions for read/write operations:A read operation will not cause an error.A non-transition write operation will not cause a fault.A transition write operation may ca

10、use a fault.第47页/共62页A Pattern Sensitive Fault (PSF) is defined as follows: The contents of a cell, or the ability to change the contents, is influenced by the contents of all other cells in the memory.The PSF can be considered the most general case of the k-coupling fault.The PSF model allows the n

11、eighborhood to take on any position in the memory array.When the neighborhood is allowed to take on only a single position, one speaks about a Neighborhood Pattern Sensitive Fault (NPSF).第48页/共62页 READ0/READALL+EMBERASE+BLANK PRGDIAG VERDIAG PRGRVCK RVCKSP PRGSP1 / 2 PRGCKBD第49页/共62页These test block

12、s work together to insure the array is blank before testing continues. A portion of the array is read using READ0 or READALL (depending on the flow). Devices which fail this initial blank check are PREERASE, and then the erase is verified with a full Blank Check.Description: 第50页/共62页PRGDIAG Embedde

13、d Programs a reverse DIAG pattern. Each byte/word must program within SPECHot temperature is worst-case since column leakage is at its highest levels.Only the programmed 0s are verified at this test block. Description:00 01 10 11000110110000第51页/共62页Reads both 1s and 0s of the DIAG pattern. The DIAG

14、 pattern is designed to reveal metal shorts (M1-M1, M1-M2, and M2-M2) which cause blank bits to program adjacent to the target programming bit. Programming only one bit per column helps reveal this type of defect.In Figure , the array on the right has a metal short between columns (bitlines) 2 and 3

15、. The short accidentally shares the programming drain voltage between the two columns. The programming wordline voltage is common across a row, so programming any bit in column 2 accidentally programs the adjacent bit in column 3.Description:This is called bit pickup第52页/共62页00 01 10 110001101100000

16、000Description:RVCK is a worst-case pattern for speed since outputs switch on every address transition (1-0-1-0).第53页/共62页RVCKSP tests AC speed by reading the RVCK pattern with tight timing. There are usually six speed grades. The program tests units starting with the fastest speed bin, and moving t

17、hrough the six grades until finding a passing bin. The actual speed values of the six bins vary from program to program, depending on the speed distribution of the part and Marketing requirements.An example of 3V speed grades is shown below:Description:第54页/共62页The PRGSP1/2 blocks test the AC write

18、parameters It Embedded Programs one row and one column using tight timing parameters and address/data formatting. A programming failure indicates the write command was not accepted due to the tight write parameters.Description:第55页/共62页Programs a CKBD pattern, which alternates 1s and 0s through the

19、entire array. This checks the programmability of half the array. The surrounding blank bits are NOT read in this test, they are checked in Checkerboard Verify.Programming Checkerboard Description:第56页/共62页Reads both 1s and 0s of the CKBD pattern. The CKBD pattern is designed to reveal bit-to-bit sho

20、rts, typically caused by poly 1 to poly 1 shorts. Unlike metal shorts which affect entire columns, the poly 1 shorts only affect bits adjacent to the short. So every pair of bits must be checked. By alternating 1s and 0s through the whole array, the CKBD pattern accomplishes this task.Checkerboard V

21、erify Description:第57页/共62页Parametrics Opens, Shorts, Icc power tests, Input / Output Lkg IREF Trim * trims reference current / VT levels, accounting for temperature difference from wafer sort EMBERASE * Embedded Erases the devices if the previous test indicates non-blank VERDIAG verify DIAG pattern

22、, checking for failures due to MANDIAG PRGRVCK programs a RVCK pattern to check programmability and prepare for pattern read PRGDIAG * program DIAG pattern (usually reverse DIAG) to check programmability and prepare for pattern read BLANK * verifies the device is blank after the Embedded Erase 第58页/共62页RVCKSP * AC speed read of RVCK pattern VOLVOH * DC input / output levels PRGSP1 / 2 * address / data formatting test to check for AC write parameters CHIPSECT * erases e