EDA程序设计试题及答案

1、1请画出下段程序的真值表，并说明该电路的功能。LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY aaa ISPORT( oe,dir :IN STD_LOGIC ;a,b : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0 ) ;END aaa ;ARCHITECTURE ar OF aaa ISBEGINPROCESS(oe , dir )输入输出BEGINa1a0x3x2x1x0IF oe= 0 THEN a<=” zzzzzzzz” ;b<= ” zzzzzzzz”;000001ELSIF oe= 1 THEN

2、010010IF dir= 0 THEN b<=a;100100ELSIF dir= 1 THEN a<=b;111000ENDIF;END IF ;END PROCESS ;END ar ;功能为：2 4 译码器 .4分2请说明下段程序的功能，写出真值表，并画出输入输出波形。LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;ENTITY aaa ISPORT( reset,clk: IN STD_LOGIC;q: BUFFER

3、STD_LOGIC_VECTOR(2 DOWNTO 0);END aaa;ARCHITECTURE bd OF aaa ISBEGINPROCESS(clk,reset)BEGINIF (reset='0') THEN q<="000"ELSIF (clk'event AND clk='1') THENIF (q=5) THEN q<="000"ELSE q<=q+1;END IF;END IF;END PROCESS;END bd;功能为：带进位借位的4 位加/减法器。.3 分输入输出波形图如下

4、：7 分a3.01.试用 VHDL 语言编程实现74LS273 芯片的功能。LIBRARYUSEieee;ieee.std_logic_1164.ALL;3.ENTITYls273PORT(clr, dq);ISclkIN std_logic;IN std_logic_vector(7 DOWNTO 0 );OUT std_logic_vector(7 DOWNTO 0 );ENDls273;ARCHITECTURElock8OF ls273 IS2141BEGINPROCESS ( clk )BEGINIF (CLR= 0)THENq<=”00000000” ;ELSEIF (clk

5、event AND clk= 1) THEN q<=d;ELSEIF ( clk= 0 ) THEN q<=q;END IF;END PROCESS;END lock8;请用 VHDL 语言编程实现一个状态向量发生器。LIBRARYUSEieee;ieee.std_logic_1164.ALL;ENTITYstasPORT(IScp, rst p);INstd_logic;BUFFER std_logic_vector(7 DOWNTO 0 );ENDstas;ARCHITECTUREarstasOF stasISBEGIN12312121PROCESS (cp )1BEGINIF

6、(rst=” 0”) THEN p<=”00000000”;1ELSEIF (cp event AND cp= 1 )1WITH p SELECTp<= ”10101010”WHEN“00000000”;” 01010101 ”WHEN“10101010”;” 00001111”WHEN“01010101 ”;” 11110000”WHEN“00001111”;” 11111111”WHEN“ 11110000”;”00000000”WHEN“ 11111111”;”00000000”WHENOTHERS;6END IFEND PROCESS;END arstas;1. 阅读下段程

7、序，画出该电路的真值表，并详细说明该电路的功能。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ab_8 ISPORT( a, b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);ahb, alb, aeb: OUT STD_LOGIC);END ab_8;ARCHITECTURE bd OF ab_8 ISBEGINPROCESS(a,b)alb<= 0; aeb<= 0 ;alb<= 1 ; aeb<= 0;aeb<= 1 ;BE

8、GINIF a>b THEN ahb<=1;ELSIF a<b THEN ahb<=0;ELSE ahb<= 0; alb<=0;END IF;END PROCESS;END bd;1.( 1)真值表如下：(5)输入输出a、 bahbalbaeba>b100a<b010a=b0012）该电路是一个8 位两输入比较器，（ 2 ）a、 b 是两个 8 位输入端；（ 1 ）1”，其余端输出为“0”。 （ 2）ahb、 alb 和 aeb 为比较结果输出端，某种比较结果为真时，相应的输出端为“1. 试用 VHDL 语言编程实现一个2-4译码器，其真表如下

9、：输入端输出端enselecty0XX“1111”100“1110”101“1101 ”110“1011 ”111“0111 ”2-4 译码器码参考 程序如下：(答案不唯一，用case语句、 with select语句都可以。)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;(1)ENTITY ym24 ISPORT( en : IN STD_LOGIC;select : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)(3);END ym24;ARCHITECTURE

10、bd OF ym24 ISBEGINPROCESS(en)(1 )IF (en=1) THENy<=” 1110”WHENselect=”00”ELSE” 1101”WHENselect =” 01”ELSE” 1011”WHENselect =” 10”ELSE” 0111”WHENselect =” 11”ELSE(4)” 1111”;ELSE y<=”1111”;END PROCESS;END bd;A、 B、 C、 D、 E、 F 都是 8 位输入总2. 试用 VHDL 语言设计一个六路8 位总线复用器，其中线， Q为 8位输出总线，S为 3 位选择端，其功能如下：输入端输

11、出端S2S1S0Q7Q0000Q=A001Q=B010Q=C011Q=D100Q=E101Q=F其它B= “ 00000000”六路 8 位总线复用器参考 程序： (答案不唯一)LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY mux6 IS(1)PORT(S : IN std_logic_vector(2 DOWNTO 0);A,B,C,D,E,F: IN std_logic_vector(7 DOWNTO 0);Q: OUT std_logic_vector(7 DOWNTO 0);(3)END mux6;ARCHITECTURE bd OF

12、mux6 ISBEGINPROCESS(S)BEGIN(1 )CASE S ISWHEN "000"=>Q<=A;WHEN "001"=>Q<=B;WHEN "010"=>Q<=C;WHEN "011"=>Q<=D;WHEN "100"=>Q<=E;WHEN "101"=>Q<=F;WHEN OTHERS=>Q<="00000000"(4)END CASE;END PROC

13、ESS;END bd;10 分）2、已知三选一电路如图，判断下列程序是否有错误，如有则指出错误所在，并给出完整程序。library ieee;use ieee.std_logic_1164.all;ENTITY MAX isport(a1,a2,a3,s0,s1:in bit;outy:out bit);end max;( 2)architecture one of max iscomponent mux21aport(a,b,s:in std_logic;y:out std_logic);end component; ( 2)signal temp std_logic; ( 2 )begin

14、u1:mux21a port map(a2,a3,s0,temp); ( 2)u2:mux21a port map(a1,temp,s1,outy); ( 2)end one;1. 已知电路原理图如下，请用VHDL 语言编写其程序答： library ieee;use ieee.std_logic_1164.all;entity mux21 isport(a,b,s:in bit;y:out bit);end mux21;( 4)architecture one of mux21 issingle d,e:bit;begind<=a and (not)s;e<=b and s;y&

15、lt;=d or e;end one;2. 设计一个带有异步清零功能的十进制计数器。计数器时钟clk 上升沿有效、清零端CLRN 、进位输出co。答： library ieee;use ieee.std_logic_1164.all;entity counter10 isport(clk,CLRN:in std_logic;dout:out integer range 0 to 9);end counter10;( 5)architecture behav of counter10 IS beginprocess(clk)variable cnt:integer range 0 to 9;(

16、3)begin IF CLRN='0' THENCNT:=0;ELSIFclk='1'and clk'event thenif cnt=9 thencnt:=0;elsecnt:=cnt+1;end if;end if;dout<=cnt;end process;end behav;( 7)3. 1)用 VHDL 语言编写半加器和或门器件的程序，如图所示：答 ：半加器程序：library ieee;use ieee.std_logic_1164.all;entity h_adder isport(a,b:in std_logic;co,so:out

17、 std_logic);end h_adder;architecture one of h_adder isbeginso<=not(a xor(not b);co<=a and b;end one;或门程序：library ieee;use ieee.std_logic_1164.all;entity or2a isport(a,b:in std_logic;c:out std_logic);end or2a;architecture one of or2a isbeginc<=a or b;end one;2)在上道题目的基础上用元件例化语句设计1 位全加器。2)3)2)

18、主程序：library ieee;use ieee.std_logic_1164.all;entity f_adder isport(ain,bin,cin:in std_logic;cout,sum:out std_logic);end entity f_adder;architecture fd1 of f_adder iscomponent h_adderport(a,b:in std_logic;co,so:out std_logic);end component;( 5)component or2aport(a,b:in std_logic;c:out std_logic);end

19、component;signal d,e,f:std_logic;beginu1 : h_adder port map(a=>ain,b=>bin,co=>d,so=>e);u2 : h_adder port map(a=>e,b=>cin,co=>f,so=>sum);u3 : or2a port map(d,f,cout);end fd1;( 5)1. 试用 VHDL 语言编程实现一个总线开关，其真值表如下：输入输出enselectA0A6B0B6Y0Y6 0 x“ZZZZZZZ”10A11B1. 总线开关的参考程序如下：LIBRARY ie

20、ee;USE ieee.std_logic_1164.all;(1)ENTITY aaa ISPORT( en, select : IN STD_LOGIC ;A, B : IN STD_LOGIC_VECTOR(6 DOWNTO 0 ) ;Y : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)END aaa ;(4)ARCHITECTURE ar OF aaa ISBEGINPROCESS(en, select )BEGINIF en=0 THEN Y<= ” ZZZZZZZ ”;ELSIF en= 1 THENIF select= 0 THEN Y<=A;EL

21、SIF select= 1 THEN Y<=B;END IF;END IF ;END PROCESS ;END ar ;(5)2. 试用 VHDL 语言编程实现一个M10 计数器，要求该计数器有一个时钟输入端clk，一个复位端rst(低电平复位)，一个使能端en(高电平时允许计数)，一个“计数到”输出端cout，一个4位二进制当前计数值输出口q； cout端仅当计数满的一个时钟周期输出高电平，其余时刻全保持低电平。2. M10 计数器参考程序：LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE

22、 ieee.std_logic_unsigned.all;( 1 )ENTITY aaa ISPORT(clk, rst, en : IN STD_LOGIC;cout: OUT STD_LOGIC;q: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) );END aaa;(4)ARCHITECTURE bd OF aaa ISBEGINPROCESS(clk,reset,en)BEGINIF (rst='0') THEN q<="0000"ELSIF (clk'event AND clk='1') TH

23、ENIF en=1 THENIF (q=9) THEN q<="0000"ELSE q<=q+1;END IF;END IF;END IF;END PROCESS;END bd;(10)3请用VHDL 语言编程，用一个状态机模型实现一个七段码LED 字符发生器。该电路有一个复位输入端 RST，一个时钟输入端CP，一组七段码输出端ag。在LED 上七个段的排列位置如图所示。该电路的功能为，当复位输入端RST 为低电平时，输出端口输出全零，无显示；当RST 为高电平时，在时钟信号CP 的每个上升沿，输出端依次轮流输出5 个字符“HAPPY”的七段码（共阴极接法），周

24、而复始。3. 用 VHDL 语言编程实现一个LED 字符发生器参考 程序：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY gencIS(1)PORT( rst, cp:IN STD_LOGIC;a,b,c,d,e,f,g: OUT STD_LOGIC);(1 )END genc;ARCHITECTURE aa OF genc ISTYPE state IS(s0,s1, s2, s3, s4, s5 );SIGNAL pstate: state;SIGNAL dout: STD_LOGIC_VECTOR(6 DOWNTO 0 );( 2)BEGI

25、Npr1: PROCESS(cp, rst,)BEGINIF rst='0' THEN pstate <=s0;ELSIF ( cp'event AND cp='0' ) THENCASE pstate ISWHEN s0=> pstate <=s1;WHEN s1=> pstate <=s2;WHEN s2=> pstate <=s3;WHEN s3=> pstate <=s4;WHEN s4=> pstate <=s5;WHEN s5=> pstate <=s1;WHEN

26、OTHERS=> pstate <=s0;END CASE;END IF;END PROCESS;( 5) pr2: PROCESS(pstate)BEGINCASE state ISWHEN s0 => dout<="0000000"-无显示WHEN s1 => dout<="0110111"-“H”WHEN s2 => dout<="1110111"-“A”WHEN s3 => dout<="1100111"-“P”WHEN s4 => dout

27、<="1100111"-“P”WHEN s5 => dout<="0111011"-“Y”WHEN OTHERS=> dout<="0000000"- 无显示5)END CASE;END PROCESS;a<=dout(6); b<=dout(5); c<=dout(4); d<=dout(3); e<=dout(2); f<=dout(1); g<=dout(0);END aa;( 1)2试用VHDL 语言和进程语句，编程实现一个3-8译码器。该译码器的功能为，

28、当使能信号EN 为低电平时，输出端 Y7Y0 全为高电平(没有输出端被选中)当 EN 为高电平时，每一种ABC 的输入状态组合能惟一地选中一路输出(被选中的端输出低电平)。真值表如下：输入输出ABCENY7Y6Y5Y4Y3Y2Y1Y0000111111110001111111101010111111011011111110111100111101111101111011111110110111111111101111111×××011111111LIBRARY ieee;OF ls273 IS11std_logic_vector(7 DOWNTO 0 );11WH

29、EN“0001 ”;USE ieee.std_logic_1164.ALL;ENTITY ym38 ISPORT(a, b, c, en :INy:OUT);END ym38;ARCHITECTURE arc38BEGINPROCESS ( en ) SIGNAL din : BEGINdin<=a&b&c&en;WITH din SELECT y<= ” 11111110”21std_logic;std_logic_vector(7 DOWNTO 0 );3” 11111101” WHEN “0011”;” 11111011” WHEN “0101”;”

30、11110111” WHEN “0111”;” 11101111” WHEN “1001”;” 11011111” WHEN “1011”;” 10111111” WHEN “1101”;” 01111111” WHEN “1111”;” 11111111” WHEN OTHERS;END PROCESS;END arc38;51. 试用 VHDL 语言编程实现一个多路开关。输入输出S1S0ENA0B0A1B1A2B2A3B3XY001××××××××A0B0011××××&

31、#215;×××A1B1101××××××××A2B2111××××××××A3B3××0××××××××ZZ该电路的功能为，当选择端S0和 S1 为不同状态组合时，如果使能信号EN 为电平，输出端 X 和 Y 分别与不同的输入通道 A0B0、 A1B1、 A2B2和 A3B3接通并保持，当EN 为低电平时，

32、X、 Y 输出为高阻态。真值表如下：1. 多路开关的参考程序如下：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY mulkey ISPORT(s0,s1,en, a0,b0,a1,b1,a2,b2,a3,b3: IN std_logic;x, y : OUT std_logic_vector(7 DOWNTO 0 ););END mulkey;ARCHITECTURE armk OF mulkey ISSIGNAL sel : std_logic_vecter (1 DOWNTO 0 )BEGINsel<=s1&s0;PROCESS

33、 (en )BEGIN32ENDIF (en=0) THEN x<=Z;y<= Z ELSEIF (sel= ”00”) THENx<=a0 ;y<=b0;ELSEIF (sel=”01”) THENx<=a1 ;y<=b1;ELSEIF (sel=”10”) THENx<=a2;y<=b2;ELSEIF (sel=”11”) THENx<=a3 ;y<=b3;END IF;END PROCESS;armk;六、写VHDL程序：（ 10 分）1. 设计 10 进制加法计数器，要求含异步清0 和同步时钟使能。注意：时钟信号命名为CLK，

34、使能信号为EN，清零信号为RST，计数输出为CQ。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 ISPORT (CLK,RST,EN : IN STD_LOGIC;CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT : OUT STD_LOGIC );END CNT10;ARCHITECTURE behav OF CNT10 ISBEGINPROCESS(CLK, RST, EN)VARIABLE CQI : STD_LOGIC_VEC

35、TOR(3 DOWNTO 0);BEGIN计数器异步复位检测时钟上升沿检测是否允许计数（同步使能）允许计数, 检测是否小于9大于9，计数值清零IF RST = '1' THEN CQI := (OTHERS =>'0') ; -ELSIF CLK'EVENT AND CLK='1' THEN -IF EN = '1' THEN-IF CQI < 9 THEN CQI := CQI + 1;-ELSE CQI := (OTHERS =>'0');-END IF;END IF;END IF;计

36、数大于9，输出进位信号IF CQI = 9 THEN COUT <= '1'-ELSE COUT <= '0'END IF;CQ <= CQI; -将计数值向端口输出END PROCESS;END behav;2. 试描述一个带进位输入、输出的8 位全加器端口：A、 B 为加数，CIN 为进位输入，S 为加和，COUT 为进位输出LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDER8 ISPORT (A, B : IN STD_LOGIC_VECTOR (7 DOWNTO 0);CIN :

37、IN STD_LOGIC;COUT : OUT STD_LOGIC;S : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );END ADDER8;ARCHITECTURE ONE OF ADDER8 ISSIGNAL TS : STD_LOGIC_VECTOR (8 DOWNTO 0);BEGINTS <= ( 0 & A) + ( 0 & B) + CIN;S <= TS(7 DOWNTO 0);COUT <= TS(8);END ONE;七、VHDL程序设计：( 20分)设计一数据选择器MUX, 其系统模块图和功能表如下图所示。试采

38、用下面三种方式中的两种来描述该数据选择器MUX的结构体。(a) 用 if 语句。(b) 用 case 语句。(c) 用 when else 语句。Library ieee;Use ieee.std_logic_1164.all;选择信号输入数据输入Entity mymux isPort ( sel : in std_logic_vector(1 downto 0);Ain, Bin : in std_logic_vector(1 downto 0);Cout : out std_logic_vector(1 downto 0) );End mymux;Architecture one of m

39、ymux isBeginProcess (sel, ain, bin)BeginIf sel =“ 00 ” then cout <= ain and bin;Elsif sel =“ 01 ” then cout <= ain xor bin;Elsif sel =“ 10 ” then cout <= not ain;Else cout <= not bin;End if;End process;End one;Architecture two of mymux is BeginProcess (sel, ain, bin)BeginCase sel iswhen“

40、00 ”=>cout <=ain and bin;when“01 ”=>cout <=ain xor bin;when“10 ”=>cout <=not ain;when others => cout <= not bin;End case;End process;End two;Architecture three of mymux is“ 00 ” else“01 ” else10 ” else not bin;BeginCout <= ain and bin when sel = Ain xor bin when sel = Not

41、ain when sel =End three;设计一个7段数码显示译码器，并逐行进行解释LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY DECL7S ISPORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ;END ;ARCHITECTURE one OF DECL7S ISBEGINPROCESS( A )BEGINCASE A ISWHEN "0000" => LED7S <= &quo

42、t;0111111" ;WHEN "0001" => LED7S <= "0000110" ;WHEN "0010" => LED7S <= "1011011" ;WHEN "0011" => LED7S <= "1001111" ;WHEN "0100" => LED7S <= "1100110" ;WHEN "0101" => LED7S <=

43、 "1101101" ;WHEN "0110" => LED7S <= "1111101" ;WHEN "0111" => LED7S <= "0000111" ;WHEN "1000" => LED7S <= "1111111" ;WHEN "1001" => LED7S <= "1101111" ;WHEN "1010" => LED7S

44、<= "1110111" ;WHEN "1011" => LED7S <= "1111100" ;WHEN "1100" => LED7S <= "0111001" ;WHEN "1101" => LED7S <= "1011110" ;WHEN "1110" => LED7S <= "1111001" ;WHEN "1111" => L

45、ED7S <= "1110001" ;WHEN OTHERS => NULL ;END CASE ;END PROCESS ;END ;关于数据选择器饿设计1 、 4 选 1 多路选择器的IF 语句描述library ieee;use ieee.std_logic_1164.all;entity multiplexers_1 is port (a, b, c, d : in std_logic;s : in std_logic_vector (1 downto 0);o : out std_logic);end multiplexers_1;architectu

46、re archi of multiplexers_1 is beginprocess (a, b, c, d, s)beginif (s = "00") then o <= a;elsif (s = "01") then o <= b;elsif (s = "10") then o <= c;else o <= d;end if;end process;end archi;2 、 4选 1多路选择器的CASE语句描述library ieee;use ieee.std_logic_1164.all;entity

47、multiplexers_2 isport (a, b, c, d : in std_logic;s : in std_logic_vector (1 downto 0);o : out std_logic);end multiplexers_2;architecture archi of multiplexers_2 isbeginprocess (a, b, c, d, s)begincase s iswhen "00" => o <= a;when "01" => o <= b;when "10" =&g

48、t; o <= c;when others => o <= d;end case;end process;end archi;3、用选择用条件信号赋值语句描述四选一电路entity mux4 isport(i0, i1, i2, i3 : in std_logic;sel: in std_logic_vector(1 downto 0); q : out std_logic);end mux4;Architecture rtl of mux4 isbeginq<=i0 when sel =“ 00 ”elsei1 when sel =“ 01 ”elsei2 when

49、sel =“ 10”elsei3 when sel =“ 11”;end rtl;4、信号赋值语句描述四选一电路entity mux4 isport(i0, i1, i2, i3 : in std_logic;sel: in std_logic_vector(1 downto 0);q : out std_logic);end mux4;architecture rtl of mux4 issignal sel : std_logic_vector (1 downto 0); beginwith sel selectq<=i0 when sel =“ 00i1 whensel =“01

50、”,i2 whensel =“10 ”,i3 whensel =“11 ”, X when others end rtl;关于编码器和译码器的设计1 、顺序描述语句中if 语句之 8-3 线编码器library ieee;use ieee.std_logic_1164.all;entity priority_encoder isport ( sel : in std_logic_vector (7 downto 0); code :out std_logic_vector (2 downto 0); end priority_encoder;architecture archi of prio

51、rity_encoder isBeginProcess (sel)BeginIf sel(0)='1' then code<="000"Elsif sel(1)='1' then code<="001"Elsif sel(2)='1' then code<="010"Elsif sel(3)='1' then code<="011"Elsif sel(4)='1' then code<="100&

52、quot;Elsif sel(5)='1' then code<="101"Elsif sel(6)='1' then code<="110"Else code<="111"End if;End process;End archi;2、并发描述语句之8-3 线编码器library ieee;use ieee.std_logic_1164.all;entity priority_encoder_1 isport ( sel : in std_logic_vector (7 downto

53、0);code :out std_logic_vector (2 downto 0);end priority_encoder_1;architecture archi of priority_encoder_1 is begincode <= "000" when sel(0) = '1' else"001" when sel(1) = '1' else"010" when sel(2) = '1' else"011" when sel(3) = '1

54、' else"100" when sel(4) = '1' else"101" when sel(5) = '1' else"110" when sel(6) = '1' else"111" when sel(7) = '1' else "ZZZ"end archi;3 、顺序描述语句中case 语句之 3-8 译码器library ieee;use ieee.std_logic_1164.all;entity encode

55、r_38 isport ( sel : in std_logic_vector (2 downto 0);en : in std_logiccode :out std_logic_vector (7 downto 0);end encoder_38;architecture rtl of encoder_38 isbeginprocess (sel,en)beginif (en= 1 ) thencase sel iswhen "000" =>code <= " 00000001 "when "001" =>code

56、 <= " 00000010 "when "010" =>code <= " 00000100 "when "011" =>code <= " 00001000 "when“100" =>code <=" 00010000"when“101" =>code <=" 00100000"when“110" =>code <=" 01000000"

57、when“111" =>code <=" 10000000"when others =>code <= " 00000000 "end case;else code <= " zzzzzzzz "end if;end process;end rtl;并发描述语句之3-8 译码器library ieee;use ieee.std_logic_1164.all;entity encoder_38 isport ( sel : in std_logic_vector (2 downto 0);code

58、 :out std_logic_vector (7 downto 0);end encoder_38;architecture archi of encoder_38 isSignal sel: std_logic_vector (2 downto 0);BeginWith sel selectcode <= " 00000001" when sel="000", "00000010" when sel="001"," 00000100 " when sel= "010" ," 00001000 " when sel="011" ," 00010000 " when s