8位ALUverilog语言

1、大连理工大学城市学院FPGA实验报告实验内容：8位ALU系别班级：电子1004班学号：姓名：日期：一.设计概述：一种基于可编程逻辑器件 FPG解口硬件描述语言的 8位的ALU的设计方法。该ALU采用 层次设计方法，有寄存器模块、控制模块和显示模块组成，能实现 8位无符号数的取值、加 减和4种逻辑运算（与、或、异或、同或）。该ALU在QuartusII软件环境下进行功能仿真， 通过DE2验证。二.设计功能：1、该处理器的数据宽度为8bit ,可以实现算术加法、减法、逻辑与、逻辑或、逻辑非、逻辑与非、逻辑或非和逻辑异或等8种运算。2、用选择端opcode 2:0选才18种运算，2个操作数分别是 a

2、_r 7:0和b_r7:0,运算结果是alu_out7:0;并定义选择如下。选择端 opcode2:0运算结果解释说明000A操作数a_r7:0001B操作数b_r7:0010算术加法011算术减法100逻辑与101逻辑或110逻辑异或111逻辑同或3、使用DE2板上的3个拨码开关设置当前ALU的运算功能，再由8个拨码开关给定数据A和数据B,由一个按键key手动提供脉冲。三.设计方案：本设计共有5个模块。1)脉冲输出器(key手动脉冲)，计数依次产生4个脉冲到各个部件，第一个脉冲启动 信号。2)寄存器A,第二个脉冲来时锁存数据A,并在数码管上显示。3)寄存器B,第三个脉冲来时锁存数据B,并在数

3、码管上显示。4) 8位ALU,第四个脉冲来时进行运算，并锁存结果alu_out。5)结果显示器，将结果显示通过DE2上的数码管显示。四.程序分析：主程序模块：module alu8(clk,clk_r,rst,a,b,alu_out,opcode,sw_ab,HEX1, HEX0, HEX7, HEX6, HEX5,HEX4);input clk,rst,clk_r;input 7:0 sw_ab;input 2:0 opcode;output 6:0 HEX1, HEX0, HEX7, HEX6, HEX5, HEX4;output 7:0 a;output 7:0 b;output 7:0

4、 alu_out;regaU1(.clk(clk),.rst(rst),.sw_ab(sw_ab),.a_r(a),.clk_r(clk_r),.HEX7(HEX7),.HEX6(HEX6);regbU2(.clk(clk),.rst(rst),.sw_ab(sw_ab),.b_r(b),.clk_r(clk_r),.HEX5(HEX5),.HEX4(HEX4);alur U3(.clk(clk),.rst(rst),.a_r(a),.b_r(b),.alu_out(alu_out),.opcode(opcode);digital U4(.clk_r(clk_r),.rst(rst),.alu

5、_out(alu_out),.HEX1(HEX1),. HEX0(HEX0);endmodule第一位数A模块：module rega (clk,clk_r,rst,sw_ab,a_r,HEX7,HEX6);input 7:0 sw_ab;input clk,clk_r,rst;output 7:0 a_r;reg 7:0 a_r;output reg6:0 HEX7,HEX6;reg 3:0 cnt;always (posedge clk or negedge rst)if(!rst) cnt<=1'd0;else if(cnt=5) cnt<=1'd0;else

6、 cnt<=cnt+1'd1;always (posedge clk or negedge rst)if(!rst) a_r=0;else if(cnt=1) a_r=sw_ab;else a_r=a_r;parameter seg0=7'b1000000,seg1=7'b1111001,seg2=7'b0100100,seg3=7'b0110000,seg4=7'b0011001,seg5=7'b0010010 ,seg6=7'b0000010,seg7=7'b1111000,seg8=7'b0000000

7、,seg9=7'b0010000,sega=7'b0001000,segb=7'b0000011 ,segc=7'b1000110,segd=7'b0100001,sege=7'b0000110,segf=7'b0001110;always (posedge clk_r)case(a_r3:0)4'h0: HEX66:0=seg0;4'h1: HEX66:0=seg1;4'h2: HEX66:0=seg2;4'h3: HEX66:0=seg3;4'h4: HEX66:0=seg4;4'h5:

8、 HEX66:0=seg5;4'h6: HEX66:0=seg6;4'h7: HEX66:0=seg7;4'h8: HEX66:0=seg8;4'h9: HEX66:0=seg9;4'ha: HEX66:0=sega;4'hb: HEX66:0=segb;4'hc: HEX66:0=segc;4'hd: HEX66:0=segd;4'he: HEX66:0=sege;4'hf: HEX66:0=segf;default:HEX66:0=seg0;endcasealways (posedge clk_r)case(a

9、_r7:4)4'h0: HEX76:0=seg0;4'h1: HEX76:0=seg1;4'h2: HEX76:0=seg2;4'h3: HEX76:0=seg3;4'h4: HEX76:0=seg4;4'h5: HEX76:0=seg5;4'h6: HEX76:0=seg6;4'h7: HEX76:0=seg7;4'h8: HEX76:0=seg8;4'h9: HEX76:0=seg9;4'ha: HEX76:0=sega;4'hb: HEX76:0=segb;4'hc: HEX76:0=

10、segc;4'hd: HEX76:0=segd;4'he: HEX76:0=sege;4'hf: HEX76:0=segf;default:HEX76:0=seg0;endcaseendmodule第二位数B模块：module regb (clk,clk_r,rst,sw_ab,b_r,HEX5,HEX4);input 7:0 sw_ab;input clk,clk_r,rst;output 7:0 b_r;reg 7:0 b_r;output reg6:0 HEX5,HEX4;reg 3:0 cnt;always (posedge clk or negedge rst

11、)if(!rst) cnt<=1'd0;else if(cnt=5) cnt<=1'd0;else cnt<=cnt+1'd1;always (posedge clk or negedge rst)if(!rst) b_r=0;else if(cnt=2) b_r=sw_ab;else b_r=b_r;parameter seg0=7'b1000000,seg1=7'b1111001,seg2=7'b0100100,seg3=7'b0110000,seg4=7'b0011001,seg5=7'b00100

12、10,seg6=7'b0000010 seg7=7'b1111000,seg8=7'b0000000,seg9=7'b0010000,sega=7'b0001000,segb=7'b0000011,segc=7'b1000110,segd=7'b0100001,sege=7'b0000110,segf=7'b0001110;always (posedge clk_r)case(b_r3:0)4'h0: HEX46:0=seg0;4'h1: HEX46:0=seg1;4'h2: HEX46:0

13、=seg2;4'h3: HEX46:0=seg3;4'h4: HEX46:0=seg4;4'h5: HEX46:0=seg5;4'h6: HEX46:0=seg6;4'h7: HEX46:0=seg7;4'h8: HEX46:0=seg8;4'h9: HEX46:0=seg9;4'ha: HEX46:0=sega;4'hb: HEX46:0=segb;4'hc: HEX46:0=segc;4'hd: HEX46:0=segd;4'he: HEX46:0=sege;4'hf: HEX46:0=

14、segf;default:HEX46:0=seg0;endcasealways (posedge clk_r)case(b_r7:4)4'h0: HEX56:0=seg0;4'h1: HEX56:0=seg1;4'h2: HEX56:0=seg2;4'h3: HEX56:0=seg3;4'h4: HEX56:0=seg4;4'h5: HEX56:0=seg5;4'h6: HEX56:0=seg6;4'h7: HEX56:0=seg7;4'h8: HEX56:0=seg8;4'h9: HEX56:0=seg9;4&#

15、39;ha: HEX56:0=sega;4'hb: HEX56:0=segb;4'hc: HEX56:0=segc;4'hd: HEX56:0=segd;4'he: HEX56:0=sege;4'hf: HEX56:0=segf;default:HEX56:0=seg0;endcaseendmodule运算模块：module alur(clk,rst,alu_out,a_r,b_r,opcode,zero);output 7:0 alu_out;output zero;input 7:0 a_r,b_r;input 2:0 opcode;input cl

16、k,rst;reg 7:0 alu_out;reg 3:0 cnt;parameterquA=3'b000,quB=3'b001,ADD=3'b010,DEC=3'b011,ANDD=3'b100,XORR=3'b101,XOR=3'b110, NXOP=3'b111;assign zero=!a_r;always (posedge clk or negedge rst)if(!rst) cnt<=1'd0;else if(cnt=5) cnt<=1'd0;else cnt<=cnt+1'

17、d1;always (posedge clk or negedge rst)if(!rst) alu_out=0;else if(cnt=3) begincasex(opcode)quA: alu_out<=a_r;quB: alu_out<=b_r;ADD: alu_out<=a_r+b_r;DEC: alu_out<=a_r-b_r;ANDD: alu_out<=a_r&b_r;XORR: alu_out<=a_r|b_r;XOR: alu_out<=a_rAb_r;NXOP: alu_out<=a_rAb_r;default: al

18、u_out<=8'bxxxx_xxxx;endcaseendelse alu_out=0;endmodule结果显示模块：module digital(clk_r,rst,alu_out,HEX1,HEX0);input 7:0 alu_out;input clk_r,rst;output reg6:0 HEX1,HEX0;parameter seg0=7'b1000000,seg1=7'b1111001,seg2=7'b0100100,seg3=7'b0110000,seg4=7'b0011001,seg5=7'b0010010,

19、seg6=7'b0000010 seg7=7'b1111000,seg8=7'b0000000,seg9=7'b0010000,sega=7'b0001000,segb=7'b0000011 ,segc=7'b1000110,segd=7'b0100001,sege=7'b0000110,segf=7'b0001110;always (posedge clk_r)case(alu_out3:0)4'h0: HEX06:0=seg0;4'h1: HEX06:0=seg1;4'h2: HEX06

20、:0=seg2;4'h3: HEX06:0=seg3;4'h4: HEX06:0=seg4;4'h5: HEX06:0=seg5;4'h6: HEX06:0=seg6;4'h7: HEX06:0=seg7;4'h8: HEX06:0=seg8;4'h9: HEX06:0=seg9;4'ha: HEX06:0=sega;4'hb: HEX06:0=segb;4'hc: HEX06:0=segc;4'hd: HEX06:0=segd;4'he: HEX06:0=sege;4'hf: HEX06:0=segf;default: HEX06:0=seg0;endcasealways (posedge clk_r)case(alu_out7:4)4'h0: HEX16:0=seg0;4'h1: HEX16:0=seg1;4'h2: HEX16:0=seg2;4'h3: HEX16:0=seg3;4'h4: HEX16:0=seg4;4'h5: HEX16:0=seg5;4'h6: HEX16:0=seg6;4