最新EPWM-总结资料

1、精品文档DSP2808 之 EPWM 笔记一、 EPWM 有什么模式和功能6 个 EPWM包含子模式This guide describes the Enhanced Pulse Width Modulator (ePWM) Module. It includes an overview of the module and information about each of the sub-modules:?TB Time-Base Module?CC Counter Compare Module?AQ Action Qualifier Module?DB Dead-Band Generato

2、r Module?PC PWM Chopper (PC) Module(斩波 )?TZ Trip Zone Module?ET Event Trigger ModuleThe ePWM peripheral performs a digital to analog (DAC) function, where the duty cycle is equivalent to a DAC analog value; it is sometimes referred to as a Power DAC.the ePWM is built up from smaller single channel m

3、odules with separatere sources and that can operate together as required to form a system一个完整的 PWM 通道有两个 PWM 输出组成： EPWMxA EPWMxBThe ePWM modules are chained together via a clock synchronization scheme that allows them to operate as a single system when required. ECAP extended capture peripheral modu

4、les每个 EPWM 支持功能：1、专门的带周期和频率控制的16 位计数器2、两路 PWM 的输出( A,B )可以被配置为 Two in depe ndent PWM outputs with sin gle-edge operati on Two in depe ndent PWM outputs with dual-edge symmetric operati on One in depe ndent PWM output with dual-edge asymmetric operatio n 双边不对称操作？3、Asynchronous override control of PWM

5、 signals through software.4、Programmable phase-control support for lag or lead operation relative to other ePWM module5、Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis.6、Dead-band generation with independent rising and falling edge delay control.7、Programmable trip zone a

6、llocation of both cycle-by-cycle trip and one-shot trip on fault conditions.8、A trip condition can force either high, low, or high-impedance state logic levels at PWM output9、All events can trigger both CPU interrupts and ADC start of conversion (SOC) 如何理解10、Programmable event prescaling minimizes C

7、PU overhead on interrupts.11、PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives.The order In which the ePWM modules arc connected may differ Jrom what is shon in Figure 1-1. Section 2 2 3 2 fo-r the synchronization scheme for a particular device. Each eFWM module

8、 consist seven subriodulss and is connected 'Mthin a system via the signals sho.vn in Figure 1-2.Figure 1 -2, Submodules and Signal Connections for an ePWM ModuleEPWMxSYNClEPWMxSYNCOePVj'M moduleTirne*bBse (TB moduleCo inter-com pare (CC； TnadulePIEEPWMxTZlNT4EP'jYLTjcINT.tion-qualifier

9、(AC: mcdulsDead-band (DB moduleADCFWM-clopps r (PC) rnodul$one for each sequencer ( ET )Eve n 卜 triggEC (ET moduleT7T to T75GPlOEP'.VF.IkAEPWrdxBF'eripheral buwTrip-zone (TZ：- module精品文档通过GPIO外设，死区信号可以被设置成异步输入信号。Peripheral BusThe peripheral bus is 32-bits wide and allows both 16-bit and 32-b

10、it writes to the ePWM register file.PWM模块内部功能连接:Figure 13. ePWM Submodules and Critical Internal Signal Interconnects4个shadow模式寄存器(尽量使用shadow，保证数据安全)HRPWM (High Resolution PWM) 仅初始化。Table ePWM Module Control and Status Register Set Grouped by SubmoduleNameOffset 111Size 阳ShadowOe script ionTBCTLMOOO

11、1NoTiSubrnoduls RegibtarfiTrie-Base Control RegisterTBSTS1NaTiTiBafie Slate R自gi&tarTBPHSHR2x30021NaExtaniorr far HRP A1 M Ptiatt *agistep 2TBPHSM0031NoTime-Base Phase RegisterWCTR1NaTime-Bafie Counter RegnierTBPRD0x00051Yfl$T if G-i a £ eFflJRriisjarCMPCTLMOOT1NOCoLiFitef'CompAre Submo

12、dulB Regifttfirft Cajnter-Cdrnpare Conbci RegisterCMPAHRyoooe1NaExianirr fat HRPWM CcunlebConpa-e A Regnier 二CM PAQxC0091Y«$Ccunta'-Oinaro - Rpjieir”CWPBOxOOOA1YesCounter-Compare B Re«ierAQC TLAMKB1NflActiofbQualifier SubmoduleRegistersAdion-Qua her Central Reisler for Output A (EPWMxA

13、)ACCTLBDxOOOC1NaAden Qualifier Central Register far Output B (EPWMxBJAQSFRCMOOD1Ns叱叱d£臼卅ep ScflA-arG出”注 feg sierAQCSFRCOxOOOE1YesAdoO'Qua if firOantbiDOus S w Fbra>SeiDBCTLoooof1NaDeadend Generator Submodule RegistersDaad-Band Gen6Taio, Cent-矍自”DBREDxCCIu1NaDeadband Gtntrttor R*ing Edg*

14、Delay Count R|g*t«rDBFEDM0111NoDead-Band Generaior Fa img Edge Delay C&unt RegteiTZSEL3x20121NsTrip-Zone Submodule RegistarETrip-Zone Select RagUrTZCTL0x00141NoTrip'Zone Cbntnol Rs$*ter 丿T ZE I NTM0151NoTrip-Zine Enab e htemipt Register J1ZFLG(MM佃1NaTripZbne Fl*gRAgiKtAr 1TZCLR1NaTripon

15、e Clear RegntarlZFRCMK9161NoTrip'Zone Force R&护伯* 3ETSEL>00191NoEverrt-Triggsr Submodule RagiEtarsEvent-TriQger Selection RtsterETPSDxOOlA1NaEvent-Trigger Pm-Scaifi RagtsterETFLG伽00伯1N:£'/6iit-Tnsgdr F曲？slorETCLR3x301C1NoE'/fi nbTigger Clear RngittarETFRCM01D1NOEvenl-Tngger F

16、orce Reg SierFCCTL0x001 E1NaPWMhopper Submcdule Registars ftk'M'Chcpper Comboi&tarHRCNFG1NaHighReolUion Pulse Witfth Modulator HRPV；M) Extension Rei«ter$HRPWM Cbnfiguration Register 2 J事件管理器上的区别(2808 2812)Table 7. 230& ePWM Compared to 281 x Event Manager沖沖ePWM2B1x EV-A. EV-BTim

17、ers1&MX6l64)it-x2(EV-AX x2 (EV-6) (shared with PWM, CAP, QEPPWM12 independent 164)rt+4 independent (eCAP ri APWM mode)W ndependenl 16-bitHigh-Resolution PWM Control4 EPWMkA Channel OutputsNoCompare2 per time-baseli per time-baseTime-Base SyncYesNaPhase GcntnoiYesNOead-Band10-Uift independent fal

18、ling edge delay Independent rising edge delayRtsing edge - falling edge delayChopperYesNoTrip (Fault) Zanes&A$ign to any pwm module cyde-oycycie or one-shai Can force PWM pins high, bow, or high-impedance on trip6Hard-wired to a specific pwm 二or心 hih-impedance on tripIntemjpts6Can be pre-scEiled

19、 to all. second, or third evenl24 no pre-scalingADC Start of CcwersionCounter = zero, period, compare AP compare BCounter = zero, pehodr and compare of txpwm only、七种子模式的配置方法定义在 sys_marco.h文件中Table 2-1. Submodule Con figurati on ParametersSubmodule Configuration Parameter or OptionTime-base (TB)? Sca

20、le the timebase clock (TBCLK) relative to the system clock (SYSCLKOUT).? Configure the PWM time-base counter (TBCTR) frequency or period.? Set the mode for the time-base counter:- count-up mode: used for asymmetric PWM- count-down mode: used for asymmetric PWM- count-up-and-down mode: used for symme

21、tric PWM? Configure the time-base phase relative to another ePWM module.? Synchronize the time-base counter between modules through hardware or software.? Configure the direction (up or down) of the time-base counter after a synchronization event.? Configure how the time-base counter will behave whe

22、n the device is halted by an emulator.? Specify the source for the synchronization output of the ePWM module:- Synchronization input signal- Time-base counter equal to zero- Time-base counter equal to counter-compare B (CMPB)- No output synchronization signal generated.Counter-compare (CC)? Specify

23、the PWM duty cycle for output EPWMxA and/or output EPWMxB? Specify the time at which switching events occur on the EPWMxA or EPWMxB outputAction-qualifier (AQ)? Specify the type of action taken when a time-base or counter-compare submodule event occurs:- No action taken-Output EPWMxA and/or EPWMxB s

24、witched high-Output EPWMxA and/or EPWMxB switched low-Output EPWMxA and/or EPWMxB toggled? Force the PWM output state through software control? Configure and control the PWM dead-band through softwareDead-band (DB)? Control of traditional complementary dead -band relationship between upper and lower

25、 switches? Specify the output rising-edge-delay value? Specify the output falling-edge delay value? Bypass the dead-band module entirely. In this case the PWM waveform is passed through without modification.PWM-chopper (PC)? Create a chopping (carrier) frequency.? Pulse width of the first pulse in t

26、he chopped pulse train.? Duty cycle of the second and subsequent pulses.? Bypass the PWM-chopper module entirely. In this case the PWM waveform is passed throughwithout modification.Trip-zone (TZ)? Configure the ePWM module to react to one, all, or none of the trip -zone pins.? Specify the tripping

27、action taken when a fault occurs:-Force EPWMxA and/or EPWMxB high-Force EPWMxA and/or EPWMxB low-Force EPWMxA and/or EPWMxB to a high-impedance state-Configure EPWMxA and/or EPWMxB to ignore any trip condition.? Configure how often the ePWM will react to each trip-zone pin:-One-shot-Cycle-by-cycle?

28、Enable the trip-zone to initiate an interrupt.? Bypass the trip-zone module entirely.Even t-trigger (ET)? Enable the ePWM events that will trigger an interrupt.? En able ePWM events that will trigger an ADC start-of-c on vers ion event.? Specify the rate at which events cause triggers (every occurre

29、nee or every second or thirdoccurre nee)? Poll, set, or clear event flagsTB结构图Figure 2-1 Time-Base Submodule Block DigrarrjGenerate the following events:- CTR = PRD: Time-base cou nter equal to the specified period (TBCTR = TBPRD).This signal is generated whe never the coun ter value is equal to the

30、 active period register value.That is whe n TBCTR = TBPRD.- CTR = Zero: Time-base cou nter equal to zero (TBCTR = 0x0000).This signal is generated whenever the counter value is zero. That is when TBCTR equals 0x0000.-CTR = CMPBThis event is gen erated by the coun ter-compare submodule and used by th

31、e synchroni zati on out logicCTR_max:Time-base coun ter equal max value. (TBCTR = 0xFFFF)Tabic 2-2.Time-Base Submodule RegistersRegisterAddress offsetShadowedDes cri ptionTBCTL0x0000NoTime-Base Control RegisterTBSTS0«DQO1NoTime-Base Status RegisterTBPHSHR0x0002NaHRPWM eal&nsian Phase Regist

32、er 'TBPHS0x0003NoTime-Base Phase RegisterTBCTROwOOOiNoTime-Base Counter RegisterTBPRD0«0005YesTime-Base Period RegisterFigure 4-4. TimeBase Control Register (TBCTL)15141312|1096FREE. SOFTphsdirclkdivHSPCLKDIVR/WQRW47654IWV-0WW-0.0.13210HSPCLKDIV | SWVFSYNCSYNCOSELPRQLDFH$£NCTPlMODER/W-

33、0.0,1FWM1R/W-0RW-0RW-0RM>-11LEGEND' FVW = ResdWrile: R = Read oriy; w = walue rfterresei/*EPWM相关宏定义*/*时基控制*/=/#define PWM_PERIOD12625/PWM 计数周期#define HALF_PWM_PERIOD6312/PWM 计数周期一半#defi ne DEAD_BAND_COUNT160/ 死区时间 3.2us dead time=DEAD_BAND_COUNT/TBCLK/*计数方式*/#defi neTB_COUNT_UP0x0/增计数，增至TBPRD

34、，从零开始重计#defi neTB_COUNT_DOWN0x1/减计数，从 TBPRD减至0,再重复#defi neTB_COUNT_UPDOWN0x2/连续增减计数 PWM12356均设置为2/增至(TBPRD) value is reached.后再减到 0#defi neTB_FREEZE0x3停止/ PHSEN bit =0设置为主动模式，=1设置为从动模式 PWM1为主，其余为从#defi neTB_DISABLE0x0/ Phase loadi ng disabled#defi neTB_ENABLE0x1/ Phase loadi ng en abled/ PRDLD bit#d

35、efi ne TB_SHADOW0x0/ TBPRD is loaded from its shadow register when TBCTR is equal to zero./ A write or read to the TBPRD register accesses the shadow register.#defi ne TB_IMMEDIATE0x1/ Load the TBPRD register immediately./ A write or read to the TBPRD register directly accesses the active register./

36、 SYNCOSEL bits#defineTB_SYNC_IN0x0#defineTB_CTR_ZERO0x1#defineTB_CTR_CMPB0x26:4SYNCOSELSynchronization Output Select. These bits select the source of the EPWMxSYNCO00EPWMkSYNC:01CTR = zer-o： Time-base counter equal to zero (TBCTR = ChcODOO)10CTR = CMPB : Time-base counter equal to couniercompane B (

37、TBCTR = CMPB)11Disable EPWkSYNCO signal#defi ne TB_SYNC_DISABLE0x3/ HSPCLKDIV and CLKDIV bits#defi neTB_DIV10x0#defi neTB_DIV20x1#defi neTBDIV40x2s；?HSPCLKDIVHigh Speed Time-：b»e Clock P&s曲总 BitsThese bits dsierrnire part of ths tlma-base dock prescale Yadue” TBCLK = SYSCLKOUT / (HSPCLKDIV

38、x CLKDiV)This dvlsor emulates ths HSPCLK in tha IMS320x2B1x siem as used an ths Event Manager (EV) peripheral.000/1001(2 (cfefauit on reset010/4011100阳101/10110/12111/14/ PHSDIR bit#define TB DOWN0x0#define TB UP0x1U PHSDIRPhase Direction Bit.This bil is only used when the time-base courrtieF is- co

39、nfigured in the up-down-count mode The PHSDIR bil indicates the direction the tine-base countsr (TBCTR) will ccunl after a synchtonizslion event occurs snd 曰 new phase value is laeded horn the phase (TBPHS) register This is irmpective 戒 tiie direct ion 口f (he counter before the synchrgniizetiQn even

40、t.In Ina up-counl: and dxnsunl modes this bit is ignofBd.Count down ster the synchronizslkxi evesntCount up aher tne synchronlzatlar event./ CMPCTL (Compare Con trol)/=：/计数器重载方式#defi neCC_CTR_ZERO0x0计数器为0时，重新装载#defi neCC_CTR_PRD0x1周期匹配时，重新装载#defi neCC_CTR_ZERO_PRD0x2周期匹配或计数器为零时，重新装载#defi neCC_LD_DIS

41、ABLE0x3/禁止重新装载/ SHDWAMODE and SHDWBMODE bits#defi neCC_SHADOW0x0/ PWM12356 均设置为 shadow#defi neCC_IMMEDIATE0x1/ AQCTLA and AQCTLB (Actio n Qualifier Con trol)/=/ ZRO, PRD, CAU, CAD, CBU, CBD bits#defi neAQ_NO_ACTION 0x0/匹配时无动作（输出电平保持不变）#defi neAQ_CLEAR0x1/匹配时输出低电平#defi neAQ_SET0x2/匹配时输出高电平#defi neAQ

42、TOGGLE0x3/匹配时电平翻转/ DBCTL (Dead-Ba nd Con trol)Figure 4-13- Dead-Band Generator Control Register (DBCTL)15Reserved7R.41543 210ReservedIN MQDEPOLSELOUT MODlER-0RW-OR/W-DLEGEND: R/YV = REadWrits： R = Read Only: -n - value 却er resetFigure 2-28, Configuration Options for the Dead-Band SubmodulelEPWMxAin

43、fIDeCHJIN.MODE(10-Nt counter)(IM counter)Rising ecge daisyOurFall rg edge delayOul>10 S2 IDECTIJPOLSELREDFED1I EPWMkA| EPWMxB BCTLOUT_MODEB=WM)cBin/=/ OUT MODE bits /第0位控制 SO,第1位控制S1#define DB_DISABLE0x0/ POLSEL 和 IN MODE 不起作用/00绕开死区，EPWMxA in和EPWMxB in输出信号直接传给 PWM斩波器子模式。#defi neDBA_ENABLE0x1/01不

44、允许上升沿delay，A直接输出；下降沿 delay，B通过死区输出#defi neDBB_ENABLE0x2/10与01情况相反#defi neDB_FULL_ENABLE0x3/11 死区全部使能，The in put sig nal for the delay is determi ned by DBCTLIN_MODE/ POLSEL bits /Polarity Select Control 极性选择控制 /第 2 位控制 S2，第 3 位控制 S3#defi neDB_ACTV_HI0x0/ 默认不翻转极性#defineDB_ACTV_LOC0x1/A 翻转#defineDB_AC

45、TV_HIC0x2/B 翻转翻转极性有什么用法程序初始化为1#define DB_ACTV_LO0x3/A、B 都翻转(0)/IN MODE/第4位控制 S4,第5位控制S50x0/程序初始化为00x10x20x3/To produce classical dead-ba nd waveforms the default is EPWMxA In is the source for both #defi ne DBA_ALL#defi ne DBB_RED_DBA_FED#defi ne DBA_RED_DBB_FED#defi ne DBB_ALLvoid DisablePWM(void)v

46、oid EnablePWM(void)PWM_EN = 0;/disable PWM output all PWM forced highEPwm1Regs.DBCTL.bit.POLSEL=DB_ACTV_LOC;EPwm1Regs.DBCTL.bit.POLSEL=DB_ACTV_HI;EPwm2Regs.DBCTL.bit.POLSEL=DB_ACTV_LOC;EPwm2Regs.DBCTL.bit.POLSEL=DB_ACTV_HI;EPwm3Regs.DBCTL.bit.POLSEL=DB_ACTV_LOC;EPwm3Regs.DBCTL.bit.POLSEL=DB_ACTV_HI;

47、EPwm1Regs.DBCTL.bit.OUT_MODE=3;EPwm1Regs.DBCTL.bit.OUT_MODE=0;旁路死区EPwm2Regs.DBCTL.bit.OUT_MODE=3;EPwm2Regs.DBCTL.bit.OUT_MODE=0;旁路死区EPwm3Regs.DBCTL.bit.OUT_MODE=3;EPwm3Regs.DBCTL.bit.OUT_MODE=0;旁路死区EPwm1Regs.AQCSFRC.bit.CSFA=0;EPwm1Regs.AQCSFRC.bit.CSFA=2;EPwm1Regs.AQCSFRC.bit.CSFB=0;EPwm1Regs.AQCSFRC.bit.CSFB=2;EPwm2Regs.AQCSFRC.bit.CSFA=0;EPwm2Regs.AQCSFRC.bit.CSFA=2;EPwm2Regs.A