FPGA与CPLD实验报告

1、2FPGA与CPLD实验报告159030004 杨文忠实验一、正弦波的产生一、实验目的：1 学习Quartus II的使用；2 掌握宏单元模块定制ROM；3 掌握VHDL语言中的元件例化；4 掌握VHDL语言中的计数器的设计；5. 掌握SignalTap II的使用。二、实验条件：1. 装有Quartus II 13.0的电脑一台；2. EP4CE15F17C8实验开发板一套。三、实验原理：1.使用查表的方式计算正弦值，使用MATLAB产生ROM所需的正弦波mif文件；2.程序中根据计数器的值进行查表输出，并用modelsim和SignalTap II观察输出的结果。3.使用MATLAB产生m

2、if文件的程序如下：WIDTH=8;DEPTH=1024;ADDRESS_RADIX=DEC;DATA_RADIX=DEC;CONTENT BEGIN0:128;1:129;2:130;（数据略去）1021:126;1022:126;1023:127;End;保存为mif格式文件，或者直接使用Mif_Maker2010产生mif文件。四、实验内容：1. 使用宏单元模块定制ROM，操作步骤如下：Tools -> MegaWizars Plug-In Managerpage 1 -> Create a new custom megafunction variation -> Ne

3、xt -> MegaWizars Plug-In Managerpage 2a -> Installed Plug-In -> I/O -> Memory Complier -> ROM:1-PORT 设置好参数后，将定制的Files添加到工程中，调用Modelsim观察正选波形，观察之前需设计相应参数，时钟设置为100ns。2.使用SignalTap II逻辑分析仪分析FPGA产生的正弦波信号, SignalTap II的使用步骤如下：Tools -> SignalTap II Logic Analyzer -> 设置好之后，直接点击运行即可。五、实

4、验总结：通过本次实验学会了怎么使用使用宏单元模块定制ROM，并学会了如何使SignalTap II。8六、实验代码：library ieee; -正弦信号发生器源文件use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity sinwave is port (clk:in std_logic; -信号源时钟 dout:out std_logic_vector(7 downto 0);-8位波形数据输出end;architecture dacc of sinwave iscomponent data_rom PORT(ad

5、dress: IN STD_LOGIC_VECTOR (9 DOWNTO 0);-10位地址信号clock: IN STD_LOGIC := '1'q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);end component;signal q1:std_logic_vector(9 downto 0):="0000000000"-设定内部节点作为地址计算器beginprocess(clk)beginif clk'event and clk ='1' then q1<=q1+1;-q1作为地址发生器计算器

6、end if;end process;u1:data_rom port map(address=>q1,q=>dout,clock=>clk);-例化end;实验二、数字钟的设计一、实验目的：1 熟练掌握Quartus II的使用；2 掌握宏单元模块定制ROM；3 掌握VHDL语言中的元件例化；4 掌握VHDL语言中的数字钟的设计；5. 练习使用VHDL写状态机程序。二、实验条件：1. 装有Quartus II 13.0的电脑一台；2. EP4CE15F17C8实验开发板一套。三、实验原理：1.EP4CE15F17C8开发板的系统时钟是50MHz，通过分频方式产生1Hz的标准

7、秒脉冲，通过把三个计数器级联，分别对电子钟的秒分时进行计数，计数器的模分别为60,60,24；2.对计数结果进行二进制到8421BCD码的转换，通过译码器把BCD码转换成七段码，显示是通过位码控制来进行动态显示的；3.本开发板使用的按键是独立式按键，总共有六个按键，上下键完成状态间的切换，左右键完成数字的加减，中间键为确认键，还有一个单独的复位键；5.通过按键来完成当前时间和闹钟的时间调整。四、实验内容：1.计数器的设计在本次实验中使用了较多的计数器，通过编写通用计数器，再在主程序中多次例化，以达到精简代码的目的。本计数器定义了置数使能和置数值输入口来完成当前时钟时间的调节。时钟的位数和模值可

8、通过具体的例化原件来进行初始化。entity counter isgeneric (bitwidth:integer:=4;moda:integer:=12);port (clk,en,en_set:in std_logic;d :in std_logic_vector(bitwidth-1 downto 0); cout:out std_logic; counterout :out std_logic_vector(bitwidth-1 downto 0);end entity;计数器的cout是计数进位端，作为下一级计数器的计数使能端，此处需要注意本级的进位端不能作为下一级的时钟信号使，因

9、为进位端的毛刺会使计数结果出现错误。2.按键去抖程序的设计实验中需要对按键进行消抖处理，消抖的程序是直接采用计数器计数的形式，等计数器达到一定的值时，将相应的按键使能信号置为有效位。设置计数器的最大计数值为5000000，当按键按下时间到100ms时，将按键使能信号置位。调节时间和闹钟时间的程序采用状态机的方法设计。状态转换如下现态key_rst_enkey_ok_enkey_up_enkey_down_enkey_left_enkey_right_enS0S5S1S0S0S0S0S1S5S5S4S2S1S1S2S5S5S1S3S2S2S3S5S5S2S4S3S3S4S5S5S3S1S4S4S

10、5S0S0是空闲状态，在没有按键按下时在此状态，S1是分钟调节状态，S2是小时调节状态，S3是闹钟分钟调节状态，S4是闹钟小时调节状态，S5是置数使能端使能状态，此状态停留一个系统时钟后自动返回S0状态。3. 译码器的设计 本设计的译码器包括两类译码器：（1）将二进制数转换成8421BCD码；（2）将BCD码转换成七段码。4.在调节时间的时候为了显示现在正在调节的时间，在程序中加入显示控制端，显示控制端共四位，说明如下：调节内容disply_ctrl分钟调节1010小时调节1011闹铃分钟调节1110闹铃小时调节1111当正在调节时间时，让秒显示00，当调节闹铃时间时，让秒显示55，在主程序中

11、显示控制程序如下：if disply_ctrl(3 downto 2)="10" then-有键按下hour_display<=hour_set;minute_display<=minute_set;second_display<="000000"elsif disply_ctrl(3 downto 2)="11" thenhour_display<=hour_alarm;minute_display<=minute_alarm;second_display<="110111"e

12、lsehour_display<=hour;minute_display<=minute;second_display<=second;end if;为了便于观察正在设置的是分钟还是小时，使正在设置的部分以2Hz的频率闪烁显示，处理方法如下：case cnt8 iswhen "000" => if disply_ctrl(1 downto 0)="11" thenbt <= "111110" or ("11111" & clk_0_5s_duty_50 ); elsebt &l

13、t;= "111110"end if;a<=no1;when "001" => if disply_ctrl(1 downto 0)="11" thenbt <= "111101" or ("1111" & clk_0_5s_duty_50 & '1' ); elsebt <= "111101"end if;a<=no2;when "010" => if disply_ctrl(1 dow

14、nto 0)="10" thenbt <= "111011" or ("111" & clk_0_5s_duty_50 & "11" ); elsebt <= "111011"end if;a<=no3;when "011" => if disply_ctrl(1 downto 0)="10" thenbt <= "110111" or ("11" & clk_0

15、_5s_duty_50 & "111" ); elsebt <= "110111"end if;a<=no4;when "100" => bt <= "101111" a<=no5;when "101" => bt <= "011111" a<=no6;when others => bt <= "000000" a<=15;-null;end case;6.闹铃通过对比当前时间和设定

16、的闹铃的时间，当相同时，启动蜂鸣器，主要程序如下：if hour=hour_alarm and minute=minute_alarm thenbuzzer <= '1'elsebuzzer <= '0'end if;五、实验总结：35通过动手完成了本实验的主要任务，显示时间，调节时间，闹铃功能。6、 实验代码计数器程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter isgeneric (bitwidth:integer:

17、=4;moda:integer:=12);port (clk,en,en_set:in std_logic;d :in std_logic_vector(bitwidth-1 downto 0); cout:out std_logic; counterout :out std_logic_vector(bitwidth-1 downto 0);end entity;architecture one of counter isbeginprocess(clk)variable temp:std_logic_vector(bitwidth-1 downto 0);beginif clk'e

18、vent and clk='1' thencout<='0'if en_set='0' then temp := d;cout<='0'elsif en='1' thenif temp < moda-1 then temp :=temp + '1'elsetemp :=(others=>'0');cout<='1'end if;end if;end if;counterout<=temp;end process;end;按键消抖程序

19、：library ieee;use ieee.std_logic_1164.all;entity key_detect isgeneric (N:integer:=5);port (clk : in std_logic;key_rst : in std_logic;key_ok : in std_logic;key_up : in std_logic;key_down : in std_logic;key_left : in std_logic;key_right : in std_logic;key_rst_en : out std_logic;key_ok_en : out std_log

20、ic;key_up_en : out std_logic;key_down_en : out std_logic;key_left_en : out std_logic;key_right_en : out std_logic);end entity key_detect;architecture one of key_detect issignal key_all : std_logic_vector (5 downto 0);-将输入输出并行操作signal key_all_en : std_logic_vector (5 downto 0);signal key_and : std_lo

21、gic;-输入相与beginprocess(clk)variable count : integer range 0 to 500000;beginkey_all <= key_rst & key_ok & key_up & key_down & key_left & key_right;key_and <= key_rst and key_ok and key_up and key_down and key_left and key_right;if clk'event and clk='1' thenif key_

22、and='0' thenif count=N then count:=count;else count:=count+1;end if;if count=N-1 then key_all_en<=key_all;else key_all_en<="111111"end if;else count:=0;key_all_en<="111111"end if;end if;key_rst_en <= key_all_en(5);key_ok_en <= key_all_en(4);key_up_en <=

23、key_all_en(3);key_down_en <= key_all_en(2);key_left_en <= key_all_en(1);key_right_en <= key_all_en(0);end process;end architecture one;当前时间及闹钟时间设置程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity time_set isport (clk : in std_logic;key_rst_en : in std_logic;

24、key_ok_en : in std_logic;key_up_en : in std_logic;key_down_en : in std_logic;key_left_en : in std_logic;key_right_en : in std_logic;minute : in std_logic_vector(5 downto 0);-当前的时间和闹钟时间hour : in std_logic_vector(4 downto 0);minute_set : out std_logic_vector(5 downto 0);-分别为秒分时的设置单元hour_set : out std_

25、logic_vector(4 downto 0);minute_alarm : out std_logic_vector(5 downto 0);hour_alarm : out std_logic_vector(4 downto 0);en_set : out std_logic;disply_ctrl : out std_logic_vector(3 downto 0);end entity time_set;architecture one of time_set isconstant s0 : integer := 0;-空闲状态constant s1 : integer := 1;-

26、设置计数时间的分钟constant s2 : integer := 2;-设置计数时间的小时constant s3 : integer := 3;-设置闹钟时间的分钟constant s4 : integer := 4;-设置闹钟时间的小时constant s5 : integer := 5;beginp1:process(clk)variable state : integer range 0 to 8;-当前状态机的状态variable minute_set_temp : std_logic_vector(5 downto 0);-分别为秒分时的设置单元variable hour_set_

27、temp : std_logic_vector(4 downto 0);variable minute_a_set_temp : std_logic_vector(5 downto 0);variable hour_a_set_temp : std_logic_vector(4 downto 0);beginif clk'event and clk='1' thencase state iswhen s0 => en_set <= '1'-复位低电平有效if key_rst_en='0' then -有复位键按下minute_

28、set_temp := "000000"-对时间进行复位hour_set_temp := "00000"minute_a_set_temp:= "000000"hour_a_set_temp := "00000"-en_set <= '0'-复位低电平有效state := s5;elsif key_ok_en='0' then -有设置键按下minute_set_temp := minute;-读取当前的时间hour_set_temp := hour;disply_ctrl &

29、lt;= "1010"-显示控制state := s1;end if;when s1 => en_set <= '1'-复位低电平有效if key_rst_en='0' then -有复位键按下minute_set_temp := "000000"-对时间进行复位hour_set_temp := "00000"minute_a_set_temp:= "000000"hour_a_set_temp := "00000"-en_set <= '

30、;0'-复位低电平有效state := s5;elsif key_ok_en='0' then-退出设置minute_set <= minute_set_temp;hour_set <= hour_set_temp;minute_alarm <= minute_a_set_temp;hour_alarm <= hour_a_set_temp;-en_set <= '0'-复位低电平有效disply_ctrl <= "0000"state := s5;elsif key_up_en='0

31、9; then-跳至闹钟小时设置disply_ctrl <= "1111"-显示控制state := s4;elsif key_down_en='0' then-跳至小时设置disply_ctrl <= "1011"-显示控制state := s2;elsif key_left_en='0' then-分钟减1if minute_set_temp>"000000" thenminute_set_temp:= minute_set_temp-'1'elseminute_s

32、et_temp:= "000000"end if;elsif key_right_en='0' then-分钟加1if minute_set_temp<"111011" thenminute_set_temp:= minute_set_temp+'1'elseminute_set_temp:= "000000"end if;end if;when s2 => en_set <= '1'-复位低电平有效if key_rst_en='0' then -有复位

33、键按下minute_set_temp := "000000"-对时间进行复位hour_set_temp := "00000"minute_a_set_temp:= "000000"hour_a_set_temp := "00000"-en_set <= '0'-复位低电平有效state := s5;elsif key_ok_en='0' then-退出设置minute_set <= minute_set_temp;hour_set <= hour_set_temp;

34、minute_alarm <= minute_a_set_temp;hour_alarm <= hour_a_set_temp;-en_set <= '0'-复位低电平有效disply_ctrl <= "0000"state := s5;elsif key_up_en='0' then-跳至分钟设置disply_ctrl <= "1010"-显示控制state := s1;elsif key_down_en='0' then-跳至闹铃分钟设置disply_ctrl <=

35、"1110"-显示控制state := s3;elsif key_left_en='0' then-小时减1if hour_set_temp>"00000" thenhour_set_temp:= hour_set_temp-'1'elsehour_set_temp:= "00000"end if;elsif key_right_en='0' then-小时加1if hour_set_temp<"10111" thenhour_set_temp:= hou

36、r_set_temp+'1'elsehour_set_temp:= "00000"end if;end if;when s3 => en_set <= '1'-复位低电平有效if key_rst_en='0' then -有复位键按下minute_set_temp := "000000"-对时间进行复位hour_set_temp := "00000"minute_a_set_temp:= "000000"hour_a_set_temp := "0

37、0000"-en_set <= '0'-复位低电平有效state := s5;elsif key_ok_en='0' then-退出设置minute_set <= minute_set_temp;hour_set <= hour_set_temp;minute_alarm <= minute_a_set_temp;hour_alarm <= hour_a_set_temp;-en_set <= '0'-复位低电平有效disply_ctrl <= "0000"state :=

38、s5;elsif key_up_en='0' then-跳至小时设置disply_ctrl <= "1011"-显示控制state := s2;elsif key_down_en='0' then-跳至闹铃小时设置disply_ctrl <= "1111"-显示控制state := s4;elsif key_left_en='0' then-闹铃分钟减1if minute_a_set_temp>"000000" thenminute_a_set_temp:= minut

39、e_a_set_temp-'1'elseminute_a_set_temp:= "000000"end if;elsif key_right_en='0' then-闹铃分钟加1if minute_a_set_temp<"111011" thenminute_a_set_temp:= minute_a_set_temp+'1'elseminute_a_set_temp:= "000000"end if;end if;when s4 => en_set <= '1

40、'-复位低电平有效if key_rst_en='0' then -有复位键按下minute_set_temp := "000000"-对时间进行复位hour_set_temp := "00000"minute_a_set_temp:= "000000"hour_a_set_temp := "00000"-en_set <= '0'-复位低电平有效state := s5;elsif key_ok_en='0' then-退出设置minute_set <

41、;= minute_set_temp;hour_set <= hour_set_temp;minute_alarm <= minute_a_set_temp;hour_alarm <= hour_a_set_temp;-en_set <= '0'-复位低电平有效disply_ctrl <= "0000"state := s5;elsif key_up_en='0' then-跳至闹钟分钟设置disply_ctrl <= "1110"-显示控制state := s3;elsif key_d

42、own_en='0' then-跳至分钟设置disply_ctrl <= "1010"-显示控制state := s1;elsif key_left_en='0' then-闹铃小时减1if hour_a_set_temp>"00000" thenhour_a_set_temp:= hour_a_set_temp-'1'elsehour_a_set_temp:= "00000"end if;elsif key_right_en='0' then-闹铃小时加1i

43、f hour_a_set_temp<"10111" thenhour_a_set_temp:= hour_a_set_temp+'1'elsehour_a_set_temp:= "00000"end if;end if;when s5 =>state := s0;en_set <= '0'-置数使能when others =>state := s0;en_set <= '1'minute_set <= minute_set_temp;hour_set <= hour

44、_set_temp;minute_alarm <= minute_a_set_temp;hour_alarm <= hour_a_set_temp;end case;minute_set <= minute_set_temp;hour_set <= hour_set_temp;minute_alarm <= minute_a_set_temp;hour_alarm <= hour_a_set_temp;end if;end process;end architecture one;二进制数转8421BCD码程序：library IEEE;use IEEE.S

45、TD_LOGIC_1164.all;entity dec_to_bcd isport(tt : in std_logic_vector(5 downto 0); led0 : out integer range 0 to 15; led1 : out integer range 0 to 15);end entity;architecture one of dec_to_bcd isbeginprocess(tt)begincase tt iswhen "000000" => led1<=0;led0<=0;-0when "000001"

46、; => led1<=0;led0<=1;-1when "000010" => led1<=0;led0<=2;-2when "000011" => led1<=0;led0<=3;-3when "000100" => led1<=0;led0<=4;-4when "000101" => led1<=0;led0<=5;-5when "000110" => led1<=0;led0<=6;

47、-6when "000111" => led1<=0;led0<=7;-7when "001000" => led1<=0;led0<=8;-8when "001001" => led1<=0;led0<=9;-9when "001010" => led1<=1;led0<=0;-10when "001011" => led1<=1;led0<=1;-11when "001100" =&

48、gt; led1<=1;led0<=2;-12when "001101" => led1<=1;led0<=3;-13when "001110" => led1<=1;led0<=4;-14when "001111" => led1<=1;led0<=5;-15when "010000" => led1<=1;led0<=6;-16when "010001" => led1<=1;led0<=7

49、;-17when "010010" => led1<=1;led0<=8;-18when "010011" => led1<=1;led0<=9;-19when "010100" => led1<=2;led0<=0;-20when "010101" => led1<=2;led0<=1;-21when "010110" => led1<=2;led0<=2;-22when "010111&quo

50、t; => led1<=2;led0<=3;-23when "011000" => led1<=2;led0<=4;-24when "011001" => led1<=2;led0<=5;-25when "011010" => led1<=2;led0<=6;-26when "011011" => led1<=2;led0<=7;-27when "011100" => led1<=2;led0&

51、lt;=8;-28when "011101" => led1<=2;led0<=9;-29when "011110" => led1<=3;led0<=0;-30when "011111" => led1<=3;led0<=1;-31when "100000" => led1<=3;led0<=2;-32when "100001" => led1<=3;led0<=3;-33when "10001

52、0" => led1<=3;led0<=4;-34when "100011" => led1<=3;led0<=5;-35when "100100" => led1<=3;led0<=6;-36when "100101" => led1<=3;led0<=7;-37when "100110" => led1<=3;led0<=8;-38when "100111" => led1<=3;

53、led0<=9;-39when "101000" => led1<=4;led0<=0;-40when "101001" => led1<=4;led0<=1;-41when "101010" => led1<=4;led0<=2;-42when "101011" => led1<=4;led0<=3;-43when "101100" => led1<=4;led0<=4;-44when "

54、101101" => led1<=4;led0<=5;-45when "101110" => led1<=4;led0<=6;-46when "101111" => led1<=4;led0<=7;-47when "110000" => led1<=4;led0<=8;-48when "110001" => led1<=4;led0<=9;-49when "110010" => led1&l

55、t;=5;led0<=0;-50when "110011" => led1<=5;led0<=1;-51when "110100" => led1<=5;led0<=2;-52when "110101" => led1<=5;led0<=3;-53when "110110" => led1<=5;led0<=4;-54when "110111" => led1<=5;led0<=5;-55when &

56、quot;111000" => led1<=5;led0<=6;-56when "111001" => led1<=5;led0<=7;-57when "111010" => led1<=5;led0<=8;-58when "111011" => led1<=5;led0<=9;-59when others => led1<=15;led0<=15;end case;end process;end architecture;BCD码转七

57、段码程序：library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity decode is Port ( a : integer range 0 to 15; sg: out std_logic_vector (6 downto 0);end entity;architecture one of decode isbegin process(a)begincase a iswhen 0 => sg<="1000000"when 1 => sg<="1111001"when 2 => sg&l

58、t;="0100100"when 3 => sg<="0110000"when 4 => sg<="0011001"when 5 => sg<="0010010"when 6 => sg<="0000010"when 7 => sg<="1111000"when 8 => sg<="0000000"when 9 => sg<="0010000"when 10 => s