单片机毕业设计论文外文翻译中英文对照：芯片STC12C5204AD的IO口配置

1、单片机毕业设计论文外文翻译中英文对照：芯片STC12C5204AD的IO口配置 Chip STC12C5204AD I/O port configuration STC12C5204AD series microcontroller its all I/O ports are controlled by the software configuration into 4 kinds of work type 4 types are respectively: quasi two-way mouth standard the 8051 output mode, push-pull output,

2、 only for input high resistance or open-drain output functions. Every mouth consists of two control register the relevant position control each pin type of work. STC12C5204AD series microcontroller to electricity reattachment shall prevail two-way mouth standard the 8051 output mode mode: 2V above h

3、igh level, 0.8 V for low level below. 1. Quasi two-way mouth output configuration Quasi two-way mouth output type can be used as output and input function but don't need to reconfigure mouth lines output state. This is because juncture lines output is 1 drive ability is very weak, allowing exter

4、nal devices will its down. When pins for low, it output driving ability, can absorb the considerable current. Quasi two-way mouth have 3 pull_up transistor adapted to different needs. In the three and one transistor, pull up transistor called weak on pull ", for 1 and paternal line registers it

5、self pins for 1 open. This pull_up provides basic drive current make prospective two-way mouth for 1 output. If a pin for 1 and output by external devices to drop down to low, pull up close and weak "very weak pull_up" maintain open position, in order to put this pin for low, strong to pul

6、l the external devices must have enough power to make pin infused current threshold voltage of a voltage to the following. Article 2 pull_up transistors, called "extremely weak on pull", 1 latch paternal line when open. When pin, the very weak suspended the pull_up source generates very we

7、ak and current will pin and high level. Article 3 pull_up transistor called "powerful pull". Juncture line latches from 0 to 1, the jumping to accelerate must pull up by logic 0 to two-way mouth logic 1 conversion. When this happened, powerful pull open about 2 machine cycle to make pins c

8、an quickly pull to the earth high level. Quasi two-way mouth output shown below. STC12C520 series microcontroller 3V device, if the user is in pins plus 5V voltage, there will be a current flow from pins, this has caused additional VDD power consumption. Accordingly, the proposal is not in quasi two

9、-way mouth mode 3V microcontroller pins to exert 5V voltage, such as the use of words, will add current limiting resistor, or using diode do input isolation, or use triode do output segregation. Quasi two-way mouth with a schmidt trigger input and a interference suppression circuit. 2. The push-pull

10、 output configuration The drop-down push-pull output configuration open-drain output and the structure and the prospective two-way mouth down same structure, but when latches is 1 provides continuous strong pull up. The push-pull model need more commonly used for driving current situation. The push-

11、pull pins configuration are shown below. 3. Only for input high resistance configuration Input port configuration are shown below. Input port with a schmidt trigger input and a interference suppression circuit. 4. Open-drain output configuration Juncture line latches is 0, the open-drain output clos

12、e all pull_up transistors. When, as a logical output, this configuration mode must have externally pull, usually by resistance receiving V D D outside. This style of drop-down and quasi two-way mouth the same. The jammer line configuration are shown below. Open-drain port with a schmidt trigger inpu

13、t and a interference suppression circuit. A typical transistor control circuit If use weak pull_up control, suggestion plus pull-up resistors R1 3.3 K 10K, if not add pull-up resistors R 1 3.3 K 10K, suggest R2 value in the 15K above, or use a strong push-pull output.STC12C5204AD series microcontrol

14、ler programmable counter array PCA PCA contains a special 16 timer, has four 16 bits of capture/comparison of module and connected. Each module programmable work In four mode: increase/decrease along the capture, software timer, high-speed output or could be modulated pulse output. Modules connected

15、 to P3.7 0 CEX0 / PCA0 / PWM0, module 1 connected to P3.5 CEX1 / PCA1 / PWM1, modules connected to P2.0 2 CEX2 / PCA2 / PWM2, modules connected to P2.4 3 CEX3 / PCA3 / PWM3. Register the content of CH and CL is free of 16 PCA increasing count the value of the timer. PCA timer is four modules, the pu

16、blic time benchmark by programming work Programmable Counter Array PCA Timer/Counter CMOD SFR there are 2 bytes and PCA related. They were: CIDL, idle mode allows stop PCA; ECF, buy a, enabling PCA interrupt, when PCA timer spillover will PCA counting overflow marks CCON SFR CF buy bits. CCON SFR co

17、ntains PCA operating control bits CR and PCA timer mark CF and symbol of each module CCF3 / CCF2 CCF0. CCF1 / / Through the software for a CR bits CCON. 6 to run PCA. CR bit is reset when PCA closed. When PCA counter overflow, CF patients CCON. 7 buy a, if CMOD register, it produces ECF position a d

18、isruption. CF bits can only through software cleared. CCON register a 0 3 is PCA modules logo a 0 0, a corresponding module 1 corresponding module 1, bits 2 corresponding module 2, a 3 corresponding module 3, when there is a match or by hardware buy a comparisons. These signals are the only through

19、software cleared. PCA capture of patterning If CCON SFR bits of the throne of CCFn and CCAPMn SFR ECCFn bit is set position, will produce the interruption. A software timer mode Through the CCAPMn registers for a ECOM and MAT bits, can make the PCA module used for software timer below. PCA timer val

20、ues and module of the register compared to capture, when both values equal, if a CCON SFR in CCFn in and a ECCFn CCAPMn SFR in all buy bits, will produce the interruption. PCA Software Timer Mode/Software Timer model/PCA comparative Mode PCA Software Timer Mode/Software Timer model/PCA comparative M

21、ode High-speed output model This model below, when PCA counter plan of the numerical and module capture registers matching, PCA value CEXn output will happen module of the flip. To activate the high-speed output modes of CCAPMn TOG SFR, modules, MAT and ECOM bit must buy bits. PCA High - Speed, Outp

22、ut Mode/PCA high-speed Output Mode In use PCA high-speed output mode special application note: If a certain PCA module working in high speed pulse output mode, want to use software output change the same group of other common I/O port state, need to do first, whether CCAPnH judge CH is equal to abid

23、e, can freely modify, if equal, and determine CCAPnL circumstances CL is allowed to change the same group of other common I/O port state. If use P3.7 / PCA0 / PWM0 do PCA high-speed pulse output, and the program inside and with software output change when the state P3.4 mouth, you need to do judgmen

24、t. When one has the PCA high-speed pulse output function of I/O mouth working in high speed pulse output mode, if the software for the same group of other I/O port operation, if meet PCA comparator matching, this operation can change the pulse output function with PCA high-speed mouth of the I/O. PC

25、A PWM mode/modulation pulse width output mode Since all share only PCA timer modules, all their output frequency is same. The output of each module 390v is independent of the changes, and using EPCnL, captured CCAPnL of registers concerned. When CL SFR value is less than CCAPnL EPCnL, when output is

26、 low, and the value of SFR when PCA CL is equal to or greater than EPCnL, CCAPnL , the output as high. When the value of the CL by FF into EPCnH, 00 overflow, CCAPnH the contents of EPCnL, loaded into the CCAPnL . In this way, can realize update PWM without interference. To make CCAPMn PWM mode, mod

27、ule can PWMn and ECOMn bits of the register to buy bits.译文 芯片STC12C5204AD的I/O口配置 STC12C5204AD系列单片机其所有I/O口均可由软件配置成4 种工作类型4 种类型分别为:准双向口(标准8051输出模式)、推挽输出、仅为输入(高阻)或开漏输出功能。每个口由2个控制寄存器中的相应位控制每个引脚工作类型。STC12C5204AD系列单片机上电复位后为准双向口(标准8051输出模式)模式:2V 以上时为高电平,0.8V 以下时为低电平。 1.准双向口输出配置 准双向口输出类型可用作输出和输入功能而不需重新配置口线输

28、出状态。这是因为当口线输出为1时驱动能力很弱,允许外部装置将其拉低。当引脚输出为低时,它的驱动能力很强,可吸收相当大的电流。准双向口有3个上拉晶体管适应不同的需要。 在3个上拉晶体管中,有1个上拉晶体管称为“弱上拉”,当口线寄存器为1且引脚本身也为1时打开。此上拉提供基本驱动电流使准双向口输出为1。如果一个引脚输出为1而由外部装置下拉到低时,弱上拉关闭而“极弱上拉”维持开状态,为了把这个引脚强拉为低,外部装置必须有足够的灌电流能力使引脚上的电压降到门槛电压以下。 第2个上拉晶体管,称为“极弱上拉”,当口线锁存为1 时打开。当引脚悬空时,这个极弱的上拉源产生很弱的上拉电流将引脚上拉为高电平。 第

29、3个上拉晶体管称为“强上拉”。当口线锁存器由0到1跳变时,这个上拉用来加快准双向口由逻辑0到逻辑1转换。当发生这种情况时,强上拉打开约2个机器周期以使引脚能够迅速地上拉到高电平。 准双向口输出如下图所示。 STC12C520系列单片机为3V器件,如果用户在引脚加上5V电压,将会有电流从引脚流向VDD,这样导致额外的功率消耗。因此,建议不要在准双向口模式中向3V 单片机引脚施加5V电压,如使用的话,要加限流电阻,或用二极管做输入隔离,或用三极管做输出隔离。 准双向口带有一个施密特触发输入以及一个干扰抑制电路。 2 .推挽输出配置 推挽输出配置的下拉结构与开漏输出以及准双向口的下拉结构相同,但当锁

30、存器为1时提供持续的强上拉。推挽模式一般用于需要更大驱动电流的情况。 推挽引脚配置如下图所示。 3 .仅为输入(高阻)配置 输入口配置如下图所示。 输入口带有一个施密特触发输入以及一个干扰抑制电路。 4.开漏输出配置 当口线锁存器为0时,开漏输出关闭所有上拉晶体管。当作为一个逻辑输出时,这种配置方式必须有外部上拉,一般通过电阻外接到V D D 。这种方式的下拉与准双向口相同。输出口线配置如下图所示。 开漏端口带有一个施密特触发输入以及一个干扰抑制电路。 一种典型三极管控制电路 如果用弱上拉控制,建议加上拉电阻R1(3.3K10K),如果不加上拉电阻R 1(3.3K10K),建议R2的值在15K

31、以上,或用强推挽输出。STC12C5204AD系列单片机可编程计数器阵列(PCA) PCA含有一个特殊的16位定时器,有4个16位的捕获/比较模块与之相连。每个模块可编程工作。 在4 种模式下:上升/下降沿捕获、软件定时器、高速输出或可调制脉冲输出。模块0连接到P3.7(CEX0/PCA0/PWM0),模块1连接到P3.5(CEX1/PCA1/PWM1),模块2连接到P2.0(CEX2/PCA2/PWM2),模块3连接到P2.4(CEX3/PCA3/PWM3)。寄存器CH和CL的内容是正在自由递增计数的16位PCA 定时器的值。PCA定时器是4个模块的公共时间基准,可通过编程工作在:1/12振

32、荡频率、1/2振荡频率、定时器0溢出或ECI脚的输入(P3.4)。定时器的计数源由CMOD SFR 的CPS1和CPS0位来确定(见CMOD特殊功能寄存器说明)。 可编程计数器阵列 PCA定时器/计数器 CMOD SFR 还有2个位与PCA相关。它们分别是:CIDL,空闲模式下允许停止PCA;ECF,置位时,使能PCA中断,当PCA定时器溢出将PCA计数溢出标志CF(CCON SFR)置位。 CCON SFR包含PCA的运行控制位(CR)和PCA定时器标志(CF)以及各个模块的标志(CCF3/CCF2/CCF1/CCF0)。通过软件置位CR 位(CCON.6)来运行PCA。CR位被清零时PCA

33、关闭。当PCA计数器溢出时,CF位(CCON.7)置位, 如果CMOD寄存器的ECF位置位, 就产生中断。CF位只可通过软件清除。CCON 寄存器的位03是PCA各个模块的标志(位0对应模块0,位1对应模块1,位2对应模块2,位3 对应模块3),当发生匹配或比较时由硬件置位。这些标志也只能通过软件清除。所有模块共用一个中断向量。PCA的中断系统如图所示。 PCA的每个模块都对应一个特殊功能寄存器。它们分别是:模块0对应CCAPM0,模块1对应CCAPM1,模块2对应CCAPM2,模块3对应CCAPM3。特殊功能寄存器包含了相应模块的工作模式控制位。 当模块发生匹配或比较时,ECCFn位(CCA

34、PMn.0,n=0,1 ,2,3 由工作的模块决定)使能CCON SFR的CCFn标志来产生中断。 PWM(CCAPMn.1)用来使能脉宽调制模式。 当PCA计数值与模块的捕获/比较寄存器的值相匹配时,如果TOG位(CCAPMn.2)置位,模块的CEXn 输出将发生翻转。 当PCA计数值与模块的捕获/比较寄存器的值相匹配时,如果匹配位MATn(CCAPMn.3)置位,CCON 寄存器的CCFn位将被置位。 CAPNn(CCAPMn.4)和CAPPn(CCAPMn.5)用来设置捕获输入的有效沿。CAPNn位使能下降沿有效,CAPPn位使能上升沿有效。如果两位都置位,则两种跳变沿都被使能,捕获可在两种跳变沿产生。 通过置位CCAPMn寄存器的ECOMn位(CCAPMn.6)来使能比较器功能。 每个PCA模块还对应另外两个寄存器,CCAPnH和CCAPnL。当出现捕获或比较时,它们用来保存16位的计数值。当PCA模块用在PWM模式中时,它们用来控制输出的占空比。 PCA捕获模式 要使一个PCA模块工作在捕获模式(下图),寄存器CCAPMn的两位(CAPNn 和CAPPn)或其中任何一位必须置1。对模块的外部CEXn 输入(CEX0/P3.7,CEX1/P3.5,CEX2/P2.0,CEX