ADI ADP2323双输出3A降压电源解决方案_第1页
全文预览已结束

下载本文档

版权说明:本文档由用户提供并上传,收益归属内容提供方,若内容存在侵权,请进行举报或认领

文档简介

1、adi adp2323双输出3a降压电源解决方案公司的adp2323是集成了90 m的高边的双输出3a 20v同步降压电源稳压器,输入4.5v-20v,输出精度±1%,具有的输出配置,双路输出3a/3a,并联单输出6a,可编程开关频率250khz到1.2mhz,主要用在通信基础设备,网络和服务器,工业和仪表,医疗保健,dc/dc pol应用等.本文介绍了adp2323主要特性, 功能方框图,以及多种应用.the adp2323 is a full featured, dual output, step-down dc-to-dc regulator based on current-

2、mode architecture. the adp2323 integrates two high-side power mosfets and two low-side drivers for the external n-channel mosfets. the two pulse-width mod-ulation () channels can be configured to deliver dual 3 a outputs or a parallel-to-single 6 a output. the regulator operates from input voltages

3、of 4.5 v to 20 v, and the output voltage can be as low as 0.6 v.the switching frequency can be programmed between 250 khz and 1.2 mhz, or synchronized to an external clock to minimize interference in multirail applications. the dual pwm channels run 180° out of phase, thereby reducing input cur

4、rent ripple as well as reducing the size of the input capacitor.the bidirectional synchronization pin can be programmed at a 60°, 90°, or 120° phase shift, providing the possibility for a stackable multiphase power solution.the adp2323 can be set to operate in pulse-frequency modulati

5、on (pfm) mode at a light load for higher efficiency or in forced pwm for noise sensitive applications. external compensation and soft start provide design flexibility. independent enable inputs and power good outputs provide reliable power sequencing. to enhance system reliability, the device also i

6、ncludes undervoltage lockout (uvlo), overvoltage protection (ovp), overcurrent pro-tection (ocp), and thermal shutdown (tsd).the adp2323 operates over the 40 to +125 junction temperature range and is available in a 32-lead lfcsp_wq package .adp2323主要特性:input voltage: 4.5 v to 20 v±1% output acc

7、uracyintegrated 90 m typical high-side mosfetflexible output configurationdual output: 3 a/3 aparallel single output: 6 aprogrammable switching frequency: 250 khz to 1.2 mhzexternal synchronization input with programmable phase shift, or internal clock outputselectable pwm or pfm mode operationadjustable current limit for small inductorexternal compensation and soft startstartup into precharged outputadp2323应用:communications infrastructurenetworking and serversindustrial an

温馨提示

  • 1. 本站所有资源如无特殊说明,都需要本地电脑安装OFFICE2007和PDF阅读器。图纸软件为CAD,CAXA,PROE,UG,SolidWorks等.压缩文件请下载最新的WinRAR软件解压。
  • 2. 本站的文档不包含任何第三方提供的附件图纸等,如果需要附件,请联系上传者。文件的所有权益归上传用户所有。
  • 3. 本站RAR压缩包中若带图纸,网页内容里面会有图纸预览,若没有图纸预览就没有图纸。
  • 4. 未经权益所有人同意不得将文件中的内容挪作商业或盈利用途。
  • 5. 人人文库网仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对用户上传分享的文档内容本身不做任何修改或编辑,并不能对任何下载内容负责。
  • 6. 下载文件中如有侵权或不适当内容,请与我们联系,我们立即纠正。
  • 7. 本站不保证下载资源的准确性、安全性和完整性, 同时也不承担用户因使用这些下载资源对自己和他人造成任何形式的伤害或损失。

评论

0/150

提交评论