EDA技术与VHDL基础课后习题答案

1、?EDA技术及VHDL根底?课后习题答案第一章EDA技术概述一、填空题1、电子设计自动化2、非常高速集成芯片硬件描述语言3、CAD、CAE、EDA4、原理图输入、状态图输入、文本输入5、VHDL、Verilog HDL6、硬件特性二、选择题1、A2、C3、A4、D5、C6、D7、A第二章可编程逻辑器件根底一、填空题1、PLD2、Altera公司、Xilinx公司、Lattice公司3、基于反熔丝编程的 FPGA4、配置芯片二、选择题1、D2、C3、C4、D第三章VHDL程序初步程序构造一、填空题1、构造、行为、功能、接口2、库和程序包、实体、构造体、配置3、实体名、类型表、端口表、实体说明局部

2、4、构造体说明语句、功能语句5、端口的大小、实体中子元件的数目、实体的定时特性6、设计库7、元件、函数8、进程PROCESS、过程PROCEDURE9、顺序语句、并行语句二、选择题1、D2、C3、C4、B5、D6、B7、A8、C三、简答题2、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY nand_3in ISPORT(a,b,c:IN STD_LOGIC; y:OUT STD_LOGIC);END;ARCHITECTURE bhv OF nand_3in ISBEGINy<=NOT(a AND b AND c);END bhv;5、000

3、06、11110111247第四章 VHDL根底一、填空题1、顺序语句、并行语句2、跳出本次循环3、等待、信号发生变化时4、函数、过程5、值类属性、函数类属性、信号类属性、数据类型类属性、数据范围类属性6、程序调试、时序仿真7、子程序、子程序二、选择题1、B2、A3、A4、C5、B6、C7、D三、判断题1、2、3、4、5、×6、×四、简答题9、修改正确如下所示：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;UNSIGNED.ALL;ENTITY count ISPORT(clk:IN BIT; q:OUT BIT_VECTOR(7 DOW

4、NTO 0);END count;ARCHITECTURE a OF count ISBEGINPROCESS(clk)IF clk'EVENT AND clk='1' THEN q<=q+1;END PROCESS;END a;10、修改正确如下所示：SIGNAL invalue:IN INTEGERRANGE 0 TO 15;SIGNAL outvalue:OUT STD_LOGIC;CASE invalue IS WHEN 0=>outvalue<='1' WHEN 1=>outvalue<='0' W

5、HEN OTHERS=>NULL;END CASE;11、修改正确如下所示：ARCHITECTURE bhv OF com1 ISBEGINSIGNAL a,b,c:STD_LOGIC;pro1:PROCESSclkBEGINIF NOT (clk'EVENT AND clk='1') THENx<=a XOR b OR c;END IF;END PROCESS;END;12、(1)PROCESS() -此题中两条IF语句均为信号c进展可能赋值，VHDL语言不允许IF a=b THEN c<=d; END IF; IF a=4 THEN c<=d

6、+1; END IF; END PROCESS;(2)ARCHITECTURE behave OF mux IS -同时为q进展屡次可能赋值，VHDL语言不允许BEGIN q<=i0 WHEN a='0' AND b='0' ELSE '0' -WHEN ELSE语句语法错误 q<=i1 WHEN a='0' AND b='1' ELSE '0' q<=i2 WHEN a='1' AND b='0' ELSE '0' q<=i3

7、 WHEN a='1' AND b='1' ELSE '0' END behave;13、next1<=1101WHEN(a='0' AND b='0')ELSE d WHEN a='0' ELSE c WHEN b='1' ELSE1011;15、1、STD_LOGIC_UNSIGNED2、GENERIC3、IN4、width-175、counter_n6、“”7、clkEVENT AND clk=18、ELSIF9、END IF10、q<= count16、修改正确如

8、下所示：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CNT10 IS PORT ( clk: IN STD_LOGIC;q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END CNT10; ARCHITECTURE bhv OF CNT10 ISSIGNAL q1 : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS (clk)BEGINIF RISING_EDGE(clk) begin begin修改为THENIF q1 < 9 THEN -q1为STD_LOGIC数据类

9、型，而9为整型不可直接比拟q1 <= q1 + 1; -q1为STD_LOGIC数据类型，而1为整型不可直接相加ELSE q1 <= (OTHERS => '0'); END IF;END IF; END PROCESS;q <= q1;END bhv;17、使用IF语句实现LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux21 ISPORT(ain,bin,sel:IN STD_LOGIC_VECTOR(1 DOWNTO 0); cout:OUT STD_LOGIC_VECTOR(1 DOWNTO 0

10、);END;ARCHITECTURE bhv OF mux21 ISSIGNAL cout_tmp:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINPROCESS(ain,bin,sel)BEGINIF (sel="00") THEN cout_tmp<=ain OR bin;ELSIF (sel="01") THEN cout_tmp<=ain XOR bin; ELSIF (sel="10") THEN cout_tmp<=ain AND bin; ELSE cout_tmp<=ain

11、NOR bin;END IF;END PROCESS;cout<=cout_tmp;END bhv;第五章 Quartus集成开发软件初步一、填空题1、实体名2、FPGA、CPLD3、.vhd4、输入、综合、适配、仿真、下载5、RTL Viewer、Technology Map Viewer6、功能、参数含义、使用方法、硬件描述语言、模块参数设置7、mif、hex8、根目录二、选择题1、C2、D第七章有限状态机设计一、设计题1、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ztj ISPORT(clk,reset:IN STD_LOGIC

12、;in_a:IN STD_LOGIC_VECTOR(1 DOWNTO 0);out_a:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END;ARCHITECTURE bhv OF ztj ISTYPE state IS(s0,s1,s2,s3); -用枚举类型定义状态，简单直观SIGNAL current_state,next_state:state; -定义存储现态和次态的信号BEGINp1:PROCESS(clk) -状态更新进程BEGINIF clk'EVENT AND clk='1' THENIF reset='1' THE

13、N current_state<=s0;ELSE current_state<=next_state;END IF;END IF;END PROCESS;p2:PROCESS(current_state,in_a) -次态产生进程BEGINCASE current_state ISWHEN s0=>IF in_a/=00” THEN next_state<=s1; ELSE next_state<=s0; END IF;WHEN s1=>IF in_a=/'01” THEN next_state<=s2; ELSE next_state<

14、=s1; END IF;WHEN s2=>IF in_a=11” THEN next_state<=s0 ELSE next_state<=s3; END IF;WHEN s3=>IF in_a/='11' THEN next_state<=s0; ELSE next_state<=s3; END IF;WHEN OTHERS=>NULL;END CASE;END PROCESS;p3:PROCESS(current_state) BEGINCASE current_state ISWHEN s0=>out_a<='

15、0101”;WHEN s1=>out_a<=1000”;WHEN s2=>out_a<=1100”;WHEN s3=>out_a<=1101”;WHEN OTHERS=>NULL;END CASE;END PROCESS;END;2、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ztj ISPORT(clk,reset:IN STD_LOGIC;ina:IN STD_LOGIC_VECTOR(2 DOWNTO 0); outa:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END;A

16、RCHITECTURE bhv OF ztj ISTYPE state IS(s0,s1,s2,s3); -用枚举类型定义状态，简单直观SIGNAL current_state,next_state:state;BEGINp1:PROCESS(clk) -状态更新进程BEGINIF clk'EVENT AND clk='1' THENIF reset='1' THEN current_state<=s0;ELSE current_state<=next_state;END IF;END IF;END PROCESS;p2:PROCESS(cu

17、rrent_state,ina) BEGINCASE current_state ISWHEN s0=>IF ina =101” THEN outa<=0010”; ELSIF ina=111” THENouta <=1100”; END IF;IF ina =000” THEN next_state<=s1; ELSE next_state<=s0; END IF;WHEN s1=>outa<=1001”;IF ina =110” THEN next_state<=s2; ELSE next_state<=s1; END IF;WHEN

18、s2=>outa<=1111”;IF ina =011” THEN next_state<=s1; ELSIF ina =100” THEN next_state<=s2;ELSE next_state<=s3; END IF;WHEN s3=>IF ina =101” THEN outa<=1101”; ELSIF ina=011” THENouta <=1100”; END IF;IF ina =010” THEN next_state<=s0; ELSE next_state<=s1; END IF;WHEN OTHERS=>NULL;END CASE;END PROCESS;END;3、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ztj ISPORT(clk,reset:IN STD_LOGIC;ina:IN STD_LOGIC_VECTOR(1 DOWNTO 0); outa:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END;ARCHITECTURE bhv OF ztj ISTYPE state IS(s0,s1,s2,s3); -用枚举类型定义状态，简单直观SIGNAL st