Microsemi Cortex－M1 IGLOO系列开发方案

1、microsemi cortexm1 igloo系列开发方案公司的actel igloo低功耗全特性闪存能满足当今手提设备所需求的功耗,面积和成本的严格需求. igloo系于支持多达300万系数门,双端口sram高达504kb,多达6个嵌入pll和620个用户i/o,工作1.2v-1.5v,功耗低至5uw,主要用在智能手机,pda,dcam,手提工业和医疗设备,pcmcia和任何超低功耗设备.本文介绍了igloo系列主要特性,以及-m1使能igloo开发套件主要特性,方框图,材料清单和元件布局图.the actel igloo low-power fpga family of reprogra

2、mmable, full-featured flash fpgas is designed to meet the demanding power, area, and cost requirements of todays portable electronics. based on the actel nonvolatile flash technology and single-chip proasic3 fpga architecture, the 1.2 v to 1.5 v operating voltage family offers the industrys lowest p

3、ower consumptionas low as 5 w. the igloo family supports up to 3 million system gates with up to 504 kbits of true dual-port sram, up to 6 embedded plls, and up to 620 user i/os.low-power applications that require 32-bit processing can use the cortex -m1 processor without license fee or royalties in

4、 m1 igloo devices. developed specifically for implementation in fpgas, cortex-m1 offers an optimal balance between performance and size to minimize power consumption.the igloo family of flash fpgas, based on a 130-nm flash process, offers the lowest power fpga, a single-chip solution, small footprin

5、t packages, reprogrammability, and an abundance of advancedm1agl1000v2 主要特性:the flash*freeze technology used in igloo devices enables entering and exiting an ultra-low power mode that consumes as little as 5 w while retaining sram and register data. flash*freeze technology simplifies power managemen

6、t through i/o and clock management with rapid recovery to operation mode.the low power active capability (static idle) allows for ultra-low power consumption (from 12 w) while the igloo device is completely functional in the system. this allows the igloo device to control system power management bas

7、ed on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power.nonvolatile flash technology gives igloo devices the advantage of being a secure, low power, singlechip solution that is live at power-up (lapu). igloo is reprogrammable and offers time-to-market benefits at a

8、n asic-level unit cost.these features enable designers to create high-density systems using existing asic or fpga design flows and tools.igloo devices offer 1 kbit of on-chip, reprogrammable, nonvolatile flashrom storage as well as clock conditioning circuitry based on an integrated phase-locked loo

9、p (pll). the agl015 and agl030 devices have no pll or ram support. igloo devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port sram and up to 300 user i/os.m1 igloo devices support the high-performance, 32-bit cortex-m1 processor developed by arm for implementat

10、ion in fpgas. cortex-m1 is a soft processor that is fully implemented in the fpga fabric. it has a three-stage pipeline that offers a good balance between low power consumption and speed when implemented in an m1 igloo device. the processor runs the armv6-m instruction set, has a configurable nested

11、 interrupt controller, and can be implemented with or without the debug block. cortex- m1 is available for free from microsemi for use in m1 igloo fpgas.the arm-enabled devices have ordering numbers that begin with m1agl and do not support aes decryption.flash*freeze technologythe igloo device offer

12、s unique flash*freeze technology, allowing the device to enter and exit ultra-low power flash*freeze mode. igloo devices do not need additional components to turn off i/os or clocks while retaining the design information, sram content, and registers. flash*freeze technology is combined with in-syste

13、m programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. the ability of igloo v2 devices to support a wide range of core voltage (1.2 v to 1.5 v) allows further reduction in power consumption, thus achieving t

14、he lowest total system power.when the igloo device enters flash*freeze mode, the device automatically shuts off the clocks and inputs to the fpga core; when the device exits flash*freeze mode, all activity resumes and data is retained.the availability of low power modes, combined with reprogrammabil

15、ity, a single-chip and single-voltage solution, and availability of small-footprint, high pin-count packages, make igloo devices the best fit for portable electronics.features and benefitslow power1.2 v to 1.5 v core voltage support for low powersupports single-voltage system operation5 w power cons

16、umption in flash*freeze modelow power active fpga operationflash*freeze technology enables ultra-low power consumption while maintaining fpga contenteasy entry to / exit from ultra-low power flash*freeze mode high capacity15k to 1 million system gatesup to 144 kbits of true dual-port sramup to 300 u

17、ser i/osreprogrammable flash technology130-nm, 7-layer metal, flash-based processlive-at-power-up (lapu) level 0 supportsingle-chip solutionretains programmed design when powered off250 mhz (1.5 v systems) and 160 mhz (1.2 v systems) system performance in-system programming (isp) and securityisp usi

18、ng on-chip 128-bit advanced encryption standard(aes) decryption (except arm -enabled igloo devices) via jtag (ieee 1532compliant)flashlock designed to secure fpga contents high-performance routing hierarchysegmented, hierarchical routing and clock structure advanced i/o700 mbps ddr, lvds-capable i/o

19、s (agl250 and above)1.2 v, 1.5 v, 1.8 v, 2.5 v, and 3.3 v mixed-voltage operationbank-selectable i/o voltagesup to 4 banks per chipsingle-ended i/o standards: lvttl, lvcmos3.3 v / 2.5 v / 1.8 v / 1.5 v / 1.2 v, 3.3 v pci / 3.3 v pci-x , and lvcmos 2.5 v / 5.0 v inputdifferential i/o standards: lvpec

20、l, lvds, b-lvds, and mlvds (agl250 and above)wide range power supply voltage support per jesd8-b,allowing i/os to operate from 2.7 v to 3.6 vwide range power supply voltage support per jesd8-12, allowing i/os to operate from 1.14 v to 1.575 vi/o registers on input, output, and enable pathshot-swappa

21、ble and cold-sparing i/osprogrammable output slew rate and drive strengthweak pull-up/-downieee 1149.1 (jtag) boundary scan testpin-compatible packages across the igloo family clock conditioning circuit (ccc) and pllsix ccc blocks, one with an integrated pllconfigurable phase shift, multiply/divide,

22、 delay capabilities, and external feedbackwide input frequency range (1.5 mhz up to 250 mhz) embedded memory1 kbit of flashrom user nonvolatile memorysrams and fifos with variable-aspect-ratio 4,608-bit ram blocks (×1, ×2, ×4, ×9, and ×18 organizations)true dual-port sram (except ×18)arm processor support in igloo fpgasm1 igloo devicescortex -m1 soft processor available with or without debug cortex-m1使能igloo开发套件cortex-m1enabled igloo development kitthe cortex-m1enabled igloo development kit is an advanced mi