FPGA_VHDL完整频率计程序

1、- MODULE: plj_a-DESIGNER: ZHOU-CREATE DATE: 2012-03-24LIBRARY ieee;USE ieee.std_logic_1164.all;-USE ieee.std_logic_unsigned.all;- ENTITY -ENTITY plj_a ISPORT ( -input port aclr : IN STD_LOGIC ; clk50m : IN STD_LOGIC ; - 1Hz control clk_t : IN STD_LOGIC; - test pulse input -output port clk_out : OUT

2、STD_LOGIC; sm_seg, sm_dig: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END plj_a;- ARCHITECTURE -ARCHITECTURE behv OF plj_a IS-COMPONENT cnt10bPORT ( -input port ); aclr,bclr clk en : IN STD_LOGIC ; : IN STD_LOGIC ; : IN STD_LOGIC ; -output port cout q : OUT STD_LOGIC ; : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)END

3、COMPONENT cnt10b;- -4-COMPONENT sm_disp-Output ports. sm_seg, sm_dig : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) dotin: IN STD_LOGIC ; PORT ( -Input ports. sm_dat: IN STD_LOGIC_VECTOR (3 DOWNTO 0); sm_sel: IN STD_LOGIC_VECTOR (2 DOWNTO 0);-);-END COMPONENT sm_disp;-5COMPONENT sm_flashPORT ();END COMPONENT ;

4、-SIGNALclk,rst_n: IN STD_LOGIC; dot_sel: IN STD_LOGIC_VECTOR (2 DOWNTO 0); datin: IN STD_LOGIC_VECTOR (31 DOWNTO 0); sm_seg, sm_dig : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)SIGNAL en, en1,bclr,clk1hz: STD_LOGIC ;SIGNAL c1,c2,c3,c4,c5,c6,c7,c8: STD_LOGIC ;SIGNAL sub_q : STD_LOGIC_VECTOR (31 DOWNTO 0);SIGNA

5、L qout : STD_LOGIC_VECTOR (31 DOWNTO 0);BEGIN- clk=50MHz -clk1hzP1:process(clk50m)CONSTANT DIV0 :integer :=24999999;VARIABLE cnt1 :integer :=0;beginif (rising_edge(clk50m) then IF cnt1>=DIV0 THEN cnt1:=0; clk1hz<=NOT clk1hz; ELSE cnt1:=cnt1+1; END IF; end if;end process P1;- clk1hz=1Hz, en=0.5

6、hzP2:process(clk1hz)beginend if; en<=NOT en; if (rising_edge(clk1hz) thenend process P2;clk_out<= clk50m;-clk1hz; - get input pulse- control signal-P3:process(clk1hz, en)-beginbclr<=NOT clk1hz;en1<= not en; - en=> count, en1=>get data assignment- end process P3;- output,en1=>get

7、 data assignment- display when stop countP4:process(aclr,en1)beginif (aclr = '0') thenqout<=(OTHERS=>'0');elsif (rising_edge(en1) thenqout<=sub_q;end if;end process P4;uf: sm_flashPORT MAP(clk=>clk50m,rst_n=>aclr,dot_sel=>"000",datin=>qout,sm_seg=>sm

8、_seg, sm_dig=>sm_dig);u1: cnt10b PORT MAP(aclr=>aclr, bclr=>bclr, clk=>clk_t,cout=>c1,q=>sub_q(3 DOWNTO 0)en=>en,);u2: cnt10b PORT MAP( aclr=>aclr, bclr=>bclr, clk=>c1,cout=>c2,q=>sub_q(7 DOWNTO 4);u3: cnt10b PORT MAP( -input portaclr=>aclr, bclr=>bclr, clk=

9、>c2,-output portcout=>c3,q=>sub_q(11 DOWNTO 8);u4: cnt10b PORT MAP( -input portaclr=>aclr, bclr=>bclr, clk=>c3,-output portcout=>c4,q=>sub_q(15 DOWNTO 12);u5: cnt10b PORT MAP( -input portaclr=>aclr, bclr=>bclr, clk=>c4,-output portcout=>c5,q=>sub_q(19 DOWNTO 16

10、)en=>en, en=>en, en=>en, en=>en,);u6: cnt10b PORT MAP( -input port); cout=>c6,q=>sub_q(23 DOWNTO 20) aclr=>aclr, bclr=>bclr, clk=>c5, en=>en, -output portu7: cnt10b PORT MAP( -input port ); aclr=>aclr, bclr=>bclr, clk=>c6, en=>en, -output port cout=>c7,q=

11、>sub_q(27 DOWNTO 24)u8: cnt10b PORT MAP( -input port ); aclr=>aclr, bclr=>bclr, clk=>c7, en=>en, -output port cout=>c8,q=>sub_q(31 DOWNTO 28)END behv;-=-/= /Author :xsyan/Date :2012-04-06/Function :This is a LED test module. The LED will be show 1234 when reset./=module sm_flash

12、();wire 3:0sm_dat;wire 2:0sm_sel;wire dotin;/reg dotin0;reg 2:0disp_sel;reg 3:0disp_dat;reg 15:0 cnt;/*-* update the disp_sel* -*/assign sm_sel=disp_sel;always (posedge clk,negedge rst_n) /位选的扫描速度beginif(!rst_n)begin cnt <= 0; disp_sel<=3'b000; input clk,rst_n, input 2:0dot_sel, input 31:0

13、datin, output 7:0 sm_seg, sm_digendelse if(cnt14)begin cnt <= 0; disp_sel<=disp_sel+3'b001; end else begin cnt<=cnt+1'b1; endend/* - * get the data to display*- */assign dotin=(dot_sel=sm_sel) ? 1'b1 : 1'b0; assign sm_dat=disp_dat;always (posedge clk or negedge rst_n) beginc

14、ase(sm_sel)3'b000 :begin disp_dat<=datin3:0; end 3'b001 :begin disp_dat<=datin7:4; end 3'b010 :begin disp_dat<=datin11:8; end 3'b011 :begin disp_dat<=datin15:12; 3'b100 :begin disp_dat<=datin19:16; 3'b101 :begin disp_dat<=datin23:20; 3'b110 :begin disp_dat<