主板各类芯片ic芯片组和cpu introduction to agp

1、Introduction to theAccelerated Graphics Port (AGP)1VGA Basicone color pixel (RGB)DACLFBScreendirect map640480redgreenDACbluesynchronizationGraphics ChipVGA CardMapTableR G BLFBDACindirect map2ScreenLFBAPG STRUCTUREAGP is a high-performance interconnect between the core-logic chipset and the graphics

2、 controller for enhanced graphics performance for 3D applications. AGP relieves the graphics bottleneck by adding a dedicated high-speed interface directly between the chipset and the graphics controller as shown below.3APG MODEThe AGP physical interface is a point-to-point topology using 1.5 volt o

3、r 3.3 volt signaling. The baseline performance level for AGP uses a 66 MHz clock to provide a peak bandwidth of 266 MB/s.A double-clocking data technique is used to achieve twice the baseline bandwidth.Thus, AGP 2X mode provides a peak bandwidth of 533 MB/s. AGP 2X mode is a superset of the 1X mode.

4、The AGP 4X mode provides high performance levels with a peak bandwidth of 1066 MB/s. This bandwidth is achieved by using a quad clocked data transfer methodology, which allows four times as much data to be transferred every 66 MHz clock cycle. With the demand for increasing data transfer rates in hi

5、gh-speed systems, the process technologies must continually improve. AGP 4X requires a processtechnology, which is 0.35 mm or better in order to meet the tighterspecifications.AGP 4X mode is a superset to the 1X and 2X modes; thus, all components supporting AGP 4X must also support 1X and 2X modes.T

6、he AGP 8X mode doubles the data transfer rate yet again to 2.1 GB/s peak bandwidth. The data is octal-pumped from the common clock frequency of 66 MHz. In order to achieve these higher data rates across the standard AGP connector, AGP 8X mode uses a parallel-terminated bus with low signal swings of

7、about 0.8 volts,4ground referenced. The AGP 4X mode 1.5 volt I/O power supply is used for backwards compatibility for designs which wish to be universal low voltage. It is likely that a 0.25 mm or better technology will be required to meet the tightspecifications.In this chapter, the terms 1X, 2X, 4

8、X, and 8X modes refer to a specific bus electrical signaling and transfer speed according to the following table:5Transfer rate1x mode (1.5v or 3.3v) 264 MB/s2x mode (1.5v or 3.3v) 532 MB/s4x mode (1.5v) 1064 MB/s68x mode (0.8v)2.1 GB/sSignaling LevelsAGP3.0 specifies a 0.8 V voltage swing, end term

9、inated, and referenced to VSS, as opposed to AGP2.0, which specified a rail-to-rail 1.5 V series terminated voltage swing.This change permits a higher data rate and a common signaling voltage, which can be realized for multiple-generations of silicon technology. Figure as follow shows the relationsh

10、ip between the VDDQ and VSS rails and the corresponding output voltage swing.7The target VSWING level is 0.8 volts for a nominal VDDQ of 1.5 volts. The actual VSWING target is proportionally dependent on the actual VDDQ.8Voltage Characteristics of VrefVref Characteristics for AGP 2X ModeVref is a DC

11、 voltage reference signal used to set the inpuse level on the AGPbus. It is set between 0.39 Vddq and 0.41 Vddq Volts. It can be generated on the AGP compliant device or provided by the system using a simple resistor divider from Vddq. Vref can be generated at each device or one source can be used b

12、y both deviceson the bus if they are both down on the motherboard. If it isd to a componentexternally, it must stay within this range with a 10 mA DC current load from every device using Vref. Since noise may be generated from other signals coupling to Vref, proper bypassing must be provided. The sy

13、stem can provide Vref from a simple resistor divider (Figure as follow). The resistor ratio R1/R2 must be exactly 2/3. Table 5 shows some sample values of R1 and R2 for resistor tolerances of 1% and 2% with one device load current of 10mA. The tighter tolerance resistor has more margin to the Vref s

14、pecificationfor IR drop due to the load current and, therefore, can have largervalues. Ifthe Vref circuit is used to drive two AGP compliant devices, resistor values no more thanhalf theum allowed value must be used due to the doubled load current.9Vref Characteristics for AGP 4X ModeVref is set bet

15、ween 0.48Vddq and 0.521Vddq Volts for AGP 4X mode. The common mode relationship between data and Vref at the driving component can be communicated to the receiver by having the Vref generated at the driver (source generated reference). Vref is generated at the driving component using a simple resist

16、or divider network from its Vddq and Vss. Two unidirectional Vref pins are provided in the connector for delivering Vref between the add-in card component and the motherboard10component. As an example for outbound writes from the graphics master to the target, the Vref will be delivered using the un

17、idirectional pin on the connector to the target. The Vref is generated using the master components power supply Vddq and Vss using a simple resistor divider network. The voltage divider network, shown in Figure as follow,consists of an AC and DC element. The DC element is usuallyof larger resistorst

18、o minimize DC power. If 1% tolerance resistors are used, any standard value of R1 and R2 between 80 W and 2.1 kW will work. For 2% tolerance resistors, use any standard value between 80 W and 1.4 kW.For the AC elements, resistors R3 and R4 must be equal in value and 2% or bettertolerance. Their valu

19、e should be selected such that the parallelof R1, R2, R3,and R4 is about 40 W. Note that if R1 and R2 are selected to be about 80 W, the ACelement of the network is not even needed. For C1 and C2, a low ESR/ESL NPO or X7R type capacitor with a value of 0.5 nF at 4 MHz can be used for the Vref circui

20、t.11Vref Characteristics for AGP 3.0 ModeAs opposed to AGP2.0, Vref for AGP3.0 is highly recommended to be locally generated for the chipset on the motherboard and for the graphics controller on the add-in card. The method of generating VREF for and AGP3.0 mode is similar to the AGP2.0; its a simple

21、 voltage divider with a capacitor referencing this voltage to ground (see Figure 26). The value of resistors is arbitrary, as long as the reference is set to 0.35volts for Vddq at 1.5 volts, asas standard 1%tolerance resistors allow. The smallest value of the resistors depends on the acceptable curr

22、ent consumption by the divider12AGP3.0 VREF Generation Using Detect Signal CircuitsFigure as follow shows an example of a voltage divider that can be used to generate VREF from Vddq for an AGP3.0 only system.13To generate the proper Vref for a universal AGP2.0/3.0 board or add-in card, either of the

23、 following circuits shown in Figure as follow can be used. MB_DET# is generated from the motherboard and GC_DET# is generated from the add-in card.When example A or B is used on the motherboard, then the correct signal to connect is GC_DET#. When the circuit (A or B) is used in the add-in card, the

24、correct signal to connect is MB_DET#. For either of the circuits above, the VREF generated by the circuit14placed on the add-in card isd to pin A66 on the AGP connector (VREFGC).The VREF generated at the motherboard level is connected to pin B66 on the AGP connector (VREFCG). Supplying the AGP3.0 VR

25、EF to the AGP connector isrequired. Use of the VREF implementation dependent.Vddq Voltage SourcesPower to the Vddq rail may bed through the connector is optional andd by a voltage regulator or the system powersupply depending on system configuration. In the case of a 3.3V only signaling environment,

26、 the system power supply will most likely be used. In the case of a 1.5V (which is only supported in AGP 8x mode), or universal 3.3V/1.5V signaling system, a voltage regulator will most likely be used. In the universal case, the voltage level of the regulator is controlled by the TYPEDET# pin which

27、is controlled by the add-in card. The two main types of regulators that can be used for the Vddq rail are linear and switching.A linear regulator is defined as a voltage control circuit withs transistor in thecurrent path. A switching regulator is defined as a voltage control circuit with a switched

28、 inductive tank circuit used in the current path. Each type of regulator has associated advantages and disadvantages including: cost, part count, board area, response time, efficiency, and thermal dissipation. Examples of a linear and a switching regulator are shown in Figure as follow, respectively

29、:151617Theum sustained current through the AGP connector on the 3.3V rail is6A. Vddq max sustained current is significantly less at about 1.5A for both the connector AGP components.AGPMode of OperationThe mode of AGP(AGP2.0,AGP3.0) operation will be selected automatically by hardware during power-up

30、 reset and cannot be changed by software. Any mode implies the following:1. electrical signaling scheme is used.2. The speed of the interface is confirm.The motherboard and Card use the MB_DET#, GC_DET#, and TYPEDET# pins to determine mode of operation according to Table as shown below.1819AGP3.0 Co

31、nnector Pin-outsBoth Universal AGP3.0 and AGP3.0 motherboards use the same AGP connectors as AGP2.0. A few additional signals have been defined to take the place of previouslypins. Furthermore, the polarity of certain signals is different from AGP. Table as shown below contains the updated pin assig

32、nments.2021Motherboard / Add-in Card InteroperabilityInteroperability is required by AGP3.0 implementations. A box with a symbolmeans the configuration is legal while a grayed out box indicates an illegal configuration and must be excluded either by electrical or mechanical means. Table as show belo

33、w shows the matrix of compatible motherboard and add-in cards and their operating and signaling voltage.22Reset Requirements for AGP3.0 Universal systemsIn general, reset requirements have changed very little from those of the AGP interface specification. Specifically, the only changes have been to

34、require proper management for motherboard/add-in card interoperability and (for calibration purposes) to formalize the minimum amount of time that must pass after reset is de-asserted (100microseconds) before any device can initiate any type of tran system/interface reset requirements are as follows

35、:ion. AGP3.0-specific Establish if the interface signaling is to be AGP2.0 or AGP3.0 in universal platforms. The signals GC_DET# and MB_DET# should be used to make the necessary determination.TYPEDET# must also be consistent with these connector signal settings. Decode are described in Table as show

36、 below. Both the motherboard and add-in card sides need to establish the interfaces mode of operation.sIf the interface is to be AGP2.0:The motherboard (or core-logic component) must force Vrefcg to 750 mV. The add-in card (or graphics component) must force Vrefgc to 750 mV.The core-logic and graphi

37、cs components must establish proper drive strengths on-their interface upon exiting reset. Interface ownership is as defined for AGP.23-If the interface is to be AGP3.0:The motherboard (or core-logic component) must force Vrefcg to 350 mV. The add-in card (or graphics component) must force Vrefgc to

38、 350 mV.The core-logic and graphics components must establish proper drive andterminator strengths on their interface upon exiting reset. Interface ownership is as defined for AGP. To manage interoperability concerns, the following special cases/steps must be handled. When an AGP3.0-only card is plu

39、gged into an AGP2.0 slot, it must take the necessary precautions to protect its electrical interface from damage. In this configuration, the AGP3.0 card must not attempt to respond to any cycle initiated by the motherboard component. When an AGP2.0 card is plugged into an AGP3.0-only motherboard, th

40、e motherboard must remove power from VDDQ pins. Further activit on the interface should be suspended.24The drive levels for AGP2.0 and AGP3.0 around RESET are given in two Table as show below . Note that the correct level must be stable well before the end of RESET.A Universal AGP3.0 design needs to

41、 use the TYPEDET#, GC_DET# and MB_DET# to make the necessary determination of the selected signaling. The controllers may not detect these signals properly during the power up sequence, so they must be able to change the signaling on the interface as necessary during RESET.2526/NOTES1 The values und

42、er “After Reset” apply to the idle cycles that follow RESET.2 An AGP2.0 graphics device might not use these pins. They should be pulled up by the core logic, or the inputs should be disabled until it is known that the graphics chip is driving them.3 PD, Pull-down = normal AGP2.0 sustainer pull-down

43、(8KW nominal) 4 Pull-up = normal AGP2.0 sustainer pull-up (8KW nominal)5 Term = Termination impedance to ground. This is the standard AGP3.0 termination. Adefault value must be used prior to the impedance of the terminator being calibrated toguarantee a low logic level.2728/NOTE1. The values under “

44、After Reset” apply to the idle cycles that follow RESET.2. The sideband signals are optional for AGP2.0 master devices and RBF and WBF are optional for all AGP masters.3. Drive Low = Driven to AGP3.0 low value, which may be the same as the Termination.4. Drive High = Driven to AGP2.0 high value.5. Term = Termination impedance to ground. This is the standard AGP3.0 termination. A default value must be used prior to the impedance of the terminator being calibrated to guara